85xx: Add support for P2020RDB board
authorPoonam Aggrwal <poonam.aggrwal@freescale.com>
Wed, 5 Aug 2009 07:59:24 +0000 (13:29 +0530)
committerKumar Gala <galak@kernel.crashing.org>
Fri, 28 Aug 2009 22:12:38 +0000 (17:12 -0500)
The code base adds P1 & P2 RDB platforms support.
The folder and file names can cater to future SOCs of P1/P2 family.
P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series.

Tested following on P2020RDB:
1. eTSECs
2. DDR, NAND, NOR, I2C.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 files changed:
MAINTAINERS
MAKEALL
Makefile
board/freescale/p1_p2_rdb/Makefile [new file with mode: 0644]
board/freescale/p1_p2_rdb/config.mk [new file with mode: 0644]
board/freescale/p1_p2_rdb/ddr.c [new file with mode: 0644]
board/freescale/p1_p2_rdb/law.c [new file with mode: 0644]
board/freescale/p1_p2_rdb/p1_p2_rdb.c [new file with mode: 0644]
board/freescale/p1_p2_rdb/tlb.c [new file with mode: 0644]
board/freescale/p1_p2_rdb/u-boot.lds [new file with mode: 0644]
doc/README.p2020rdb [new file with mode: 0644]
include/asm-ppc/global_data.h
include/configs/P1_P2_RDB.h [new file with mode: 0644]

index 85ba8d28da7c3015e4200ace717a2f0cd73b29c6..f99eae596c14478050347d69d32962c5f98463f9 100644 (file)
 #      Board           CPU                                             #
 #########################################################################
 
+Poonam Aggrwal <poonam.aggrwal@freescale.com>
+
+       P2020RDB        P2020
+
 Greg Allen <gallen@arlut.utexas.edu>
 
        UTX8245         MPC8245
diff --git a/MAKEALL b/MAKEALL
index 65cd6d0f57a1cf4a2e6ff33dc28ac48ae68f970a..6634f09f9102f5dec9f87c8b491e81d330b29f22 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -391,6 +391,7 @@ LIST_85xx="         \
        MPC8572DS_36BIT \
        P2020DS         \
        P2020DS_36BIT   \
+       P2020RDB        \
        PM854           \
        PM856           \
        sbc8540         \
index c24df6b0faaa02729539c5010f6f31b7dcac8732..b1095e8fea7af11472889298b611194f73675fba 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -2528,6 +2528,11 @@ P2020DS_config:          unconfig
        fi
        @$(MKCONFIG) -a P2020DS ppc mpc85xx p2020ds freescale
 
+P2020RDB_config:       unconfig
+       @mkdir -p $(obj)include
+       @echo "#define CONFIG_P2020" >>$(obj)include/config.h ;
+       @$(MKCONFIG) -a P1_P2_RDB  ppc mpc85xx p1_p2_rdb freescale
+
 PM854_config:  unconfig
        @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
 
diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/p1_p2_rdb/Makefile
new file mode 100644 (file)
index 0000000..9107263
--- /dev/null
@@ -0,0 +1,52 @@
+#
+# Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS-y        += $(BOARD).o
+COBJS-y        += law.o
+COBJS-y        += tlb.o
+COBJS-y        += ddr.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+       rm -f $(OBJS) $(SOBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p1_p2_rdb/config.mk b/board/freescale/p1_p2_rdb/config.mk
new file mode 100644 (file)
index 0000000..abd64bb
--- /dev/null
@@ -0,0 +1,29 @@
+#
+# Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# p1_p2rdb board
+#
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xeff80000
+endif
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
new file mode 100644 (file)
index 0000000..9518392
--- /dev/null
@@ -0,0 +1,243 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+                                  unsigned int ctrl_num);
+
+#define DATARATE_400MHZ 400000000
+#define DATARATE_533MHZ 533333333
+#define DATARATE_667MHZ 666666666
+#define DATARATE_800MHZ 800000000
+
+#define CONFIG_SYS_DDR_CS0_BNDS                0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG      0x80014202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2    0x00000000
+#define CONFIG_SYS_DDR_INIT_ADDR       0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR   0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL    0x00000000
+#define CONFIG_SYS_DDR_ZQ_CONTROL      0x00000000
+#define CONFIG_SYS_DDR_WRLVL_CONTROL   0x00000000
+#define CONFIG_SYS_DDR_PD_CONTROL      0x00000000
+#define CONFIG_SYS_DDR_SR_CNTR         0x00000000
+#define CONFIG_SYS_DDR_RCW_1           0x00000000
+#define CONFIG_SYS_DDR_RCW_2           0x00000000
+#define CONFIG_SYS_DDR_CONTROL         0x43000000      /* Type = DDR2*/
+#define CONFIG_SYS_DDR_CONTROL_2       0x24401000
+#define CONFIG_SYS_DDR_TIMING_4                0x00000000
+#define CONFIG_SYS_DDR_TIMING_5                0x00000000
+
+#define CONFIG_SYS_DDR_TIMING_3_400    0x00010000
+#define CONFIG_SYS_DDR_TIMING_0_400    0x00260802
+#define CONFIG_SYS_DDR_TIMING_1_400    0x39355322
+#define CONFIG_SYS_DDR_TIMING_2_400    0x1f9048ca
+#define CONFIG_SYS_DDR_CLK_CTRL_400    0x02800000
+#define CONFIG_SYS_DDR_MODE_1_400      0x00480432
+#define CONFIG_SYS_DDR_MODE_2_400      0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_400    0x06180100
+
+#define CONFIG_SYS_DDR_TIMING_3_533    0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_533    0x00260802
+#define CONFIG_SYS_DDR_TIMING_1_533    0x4c47c432
+#define CONFIG_SYS_DDR_TIMING_2_533    0x0f9848ce
+#define CONFIG_SYS_DDR_CLK_CTRL_533    0x02800000
+#define CONFIG_SYS_DDR_MODE_1_533      0x00040642
+#define CONFIG_SYS_DDR_MODE_2_533      0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_533    0x08200100
+
+#define CONFIG_SYS_DDR_TIMING_3_667    0x00030000
+#define CONFIG_SYS_DDR_TIMING_0_667    0x55770802
+#define CONFIG_SYS_DDR_TIMING_1_667    0x5f599543
+#define CONFIG_SYS_DDR_TIMING_2_667    0x0fa074d1
+#define CONFIG_SYS_DDR_CLK_CTRL_667    0x02800000
+#define CONFIG_SYS_DDR_MODE_1_667      0x00040852
+#define CONFIG_SYS_DDR_MODE_2_667      0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_667    0x0a280100
+
+#define CONFIG_SYS_DDR_TIMING_3_800    0x00040000
+#define CONFIG_SYS_DDR_TIMING_0_800    0x55770802
+#define CONFIG_SYS_DDR_TIMING_1_800    0x6f6b6543
+#define CONFIG_SYS_DDR_TIMING_2_800    0x0fa074d1
+#define CONFIG_SYS_DDR_CLK_CTRL_800    0x02000000
+#define CONFIG_SYS_DDR_MODE_1_800      0x00440862
+#define CONFIG_SYS_DDR_MODE_2_800      0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_800    0x0a280100
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
+       .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+       .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+       .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+       .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400,
+       .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400,
+       .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400,
+       .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400,
+       .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+       .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+       .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400,
+       .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400,
+       .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+       .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400,
+       .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+       .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400,
+       .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+       .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+       .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+       .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+       .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+       .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+       .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
+       .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+       .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+       .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
+       .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+       .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+       .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+       .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533,
+       .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533,
+       .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533,
+       .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533,
+       .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+       .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+       .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533,
+       .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533,
+       .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+       .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533,
+       .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+       .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533,
+       .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+       .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+       .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+       .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+       .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+       .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+       .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
+       .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+       .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+       .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
+       .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+       .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+       .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+       .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
+       .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
+       .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
+       .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
+       .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+       .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+       .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
+       .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
+       .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+       .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
+       .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+       .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
+       .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+       .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+       .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+       .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+       .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+       .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+       .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
+       .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+       .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+       .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+       .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+       .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+       .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+       .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+       .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+       .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+       .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+       .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+       .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+       .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+       .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+       .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+       .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+       .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+       .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+       .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+       .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+       .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+       .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+       .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+       .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+       .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
+       .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+       .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+       .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram (void)
+{
+       sys_info_t sysinfo;
+       char buf[32];
+
+       get_sys_info(&sysinfo);
+       printf("Configuring DDR for %s MT/s data rate\n",
+                               strmhz(buf, sysinfo.freqDDRBus));
+
+       if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
+               fsl_ddr_set_memctl_regs(&ddr_cfg_regs_400, 0);
+       else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
+               fsl_ddr_set_memctl_regs(&ddr_cfg_regs_533, 0);
+       else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
+               fsl_ddr_set_memctl_regs(&ddr_cfg_regs_667, 0);
+       else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
+               fsl_ddr_set_memctl_regs(&ddr_cfg_regs_800, 0);
+       else
+               panic("Unsupported DDR data rate %s MT/s data rate\n",
+                                       strmhz(buf, sysinfo.freqDDRBus));
+
+       return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+
+phys_size_t initdram(int board_type)
+{
+       phys_size_t dram_size = 0;
+
+       dram_size = fixed_sdram();
+       set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1);
+
+       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+       dram_size *= 0x100000;
+
+       puts("DDR: ");
+       return dram_size;
+}
diff --git a/board/freescale/p1_p2_rdb/law.c b/board/freescale/p1_p2_rdb/law.c
new file mode 100644 (file)
index 0000000..12d2bf4
--- /dev/null
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+       SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
+       SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+       SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
+       SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+       SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
+       SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC),
+       SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
new file mode 100644 (file)
index 0000000..4c03468
--- /dev/null
@@ -0,0 +1,222 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <tsec.h>
+#include <vsc7385.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define VSC7385_RST_SET                0x00080000
+#define SLIC_RST_SET           0x00040000
+#define SGMII_PHY_RST_SET      0x00020000
+#define PCIE_RST_SET           0x00010000
+#define RGMII_PHY_RST_SET      0x02000000
+
+#define USB_RST_CLR            0x04000000
+
+#define GPIO_DIR               0x060f0000
+
+#define BOARD_PERI_RST_SET     VSC7385_RST_SET | SLIC_RST_SET | \
+                               SGMII_PHY_RST_SET | PCIE_RST_SET | \
+                               RGMII_PHY_RST_SET
+
+#define SYSCLK_MASK    0x00200000
+#define BOARDREV_MASK  0x10100000
+#define BOARDREV_B     0x10100000
+#define BOARDREV_C     0x00100000
+
+#define SYSCLK_66      66666666
+#define SYSCLK_50      50000000
+#define SYSCLK_100     100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+       volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+       u32 val_gpdat, sysclk_gpio, board_rev_gpio;
+
+       val_gpdat = pgpio->gpdat;
+       sysclk_gpio = val_gpdat & SYSCLK_MASK;
+       board_rev_gpio = val_gpdat & BOARDREV_MASK;
+       if (board_rev_gpio == BOARDREV_C) {
+               if(sysclk_gpio == 0)
+                       return SYSCLK_66;
+               else
+                       return SYSCLK_100;
+       } else if (board_rev_gpio == BOARDREV_B) {
+               if(sysclk_gpio == 0)
+                       return SYSCLK_66;
+               else
+                       return SYSCLK_50;
+       }
+       return 0;
+}
+
+#ifdef CONFIG_MMC
+int board_early_init_f (void)
+{
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+       setbits_be32(&gur->pmuxcr,
+                       (MPC85xx_PMUXCR_SDHC_CD |
+                        MPC85xx_PMUXCR_SDHC_WP));
+       return 0;
+}
+#endif
+
+int checkboard (void)
+{
+       u32 val_gpdat, board_rev_gpio;
+       volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+       char board_rev = 0;
+       struct cpu_type *cpu;
+
+       val_gpdat = pgpio->gpdat;
+       board_rev_gpio = val_gpdat & BOARDREV_MASK;
+       if (board_rev_gpio == BOARDREV_C)
+               board_rev = 'C';
+       else if (board_rev_gpio == BOARDREV_B)
+               board_rev = 'B';
+       else
+               panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
+
+       cpu = gd->cpu;
+       printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
+       setbits_be32(&pgpio->gpdir, GPIO_DIR);
+
+/*
+ * Bringing the following peripherals out of reset via GPIOs
+ * 0 = reset and 1 = out of reset
+ * GPIO12 - Reset to Ethernet Switch
+ * GPIO13 - Reset to SLIC/SLAC devices
+ * GPIO14 - Reset to SGMII_PHY_N
+ * GPIO15 - Reset to PCIe slots
+ * GPIO6  - Reset to RGMII PHY
+ * GPIO5  - Reset to USB3300 devices 1 = reset and 0 = out of reset
+ */
+       clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
+
+       return 0;
+}
+
+int board_early_init_r(void)
+{
+       const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+       const u8 flash_esel = 2;
+
+       /*
+        * Remap Boot flash region to caching-inhibited
+        * so that flash can be erased properly.
+        */
+
+       /* Flush d-cache and invalidate i-cache of any FLASH data */
+       flush_dcache();
+       invalidate_icache();
+
+       /* invalidate existing TLB entry for flash */
+       disable_tlb(flash_esel);
+
+       set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, flash_esel, BOOKE_PAGESZ_16M, 1);
+       return 0;
+}
+
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+       struct tsec_info_struct tsec_info[4];
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       int num = 0;
+       char *tmp;
+       unsigned int vscfw_addr;
+
+#ifdef CONFIG_TSEC1
+       SET_STD_TSEC_INFO(tsec_info[num], 1);
+       num++;
+#endif
+#ifdef CONFIG_TSEC2
+       SET_STD_TSEC_INFO(tsec_info[num], 2);
+       num++;
+#endif
+#ifdef CONFIG_TSEC3
+       SET_STD_TSEC_INFO(tsec_info[num], 3);
+       if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+               tsec_info[num].flags |= TSEC_SGMII;
+       num++;
+#endif
+       if (!num) {
+               printf("No TSECs initialized\n");
+               return 0;
+       }
+#ifdef CONFIG_VSC7385_ENET
+/* If a VSC7385 microcode image is present, then upload it. */
+       if ((tmp = getenv ("vscfw_addr")) != NULL) {
+               vscfw_addr = simple_strtoul (tmp, NULL, 16);
+               printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
+               if (vsc7385_upload_firmware((void *) vscfw_addr,
+                                       CONFIG_VSC7385_IMAGE_SIZE))
+                       puts("Failure uploading VSC7385 microcode.\n");
+       } else
+               puts("No address specified for VSC7385 microcode.\n");
+#endif
+
+       tsec_eth_init(bis, tsec_info, num);
+
+       return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+       phys_addr_t base;
+       phys_size_t size;
+
+       ft_cpu_setup(blob, bd);
+
+       base = getenv_bootm_low();
+       size = getenv_bootm_size();
+
+       fdt_fixup_memory(blob, (u64)base, (u64)size);
+}
+#endif
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+       cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
new file mode 100644 (file)
index 0000000..cf9bffe
--- /dev/null
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+       /* TLB 0 - for temp stack in cache */
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+                       CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+                       CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+                       CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 0, BOOKE_PAGESZ_4K, 0),
+
+       /* TLB 1 */
+       /* *I*** - Covers boot page */
+       SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+                       0, 0, BOOKE_PAGESZ_4K, 1),
+
+       /* *I*G* - CCSRBAR */
+       SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 1, BOOKE_PAGESZ_1M, 1),
+
+       /* W**G* - Flash/promjet, localbus */
+       /* This will be changed to *I*G* after relocation to RAM. */
+       SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+                       MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+                       0, 2, BOOKE_PAGESZ_16M, 1),
+
+       /* *I*G* - PCI */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 3, BOOKE_PAGESZ_1G, 1),
+
+       /* *I*G* - PCI I/O */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 4, BOOKE_PAGESZ_256K, 1),
+
+       /* *I*G - NAND */
+       SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 5, BOOKE_PAGESZ_1M, 1),
+
+       /* *I*G - VSC7385 Switch */
+       SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 6, BOOKE_PAGESZ_1M, 1),
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p1_p2_rdb/u-boot.lds b/board/freescale/p1_p2_rdb/u-boot.lds
new file mode 100644 (file)
index 0000000..8470df7
--- /dev/null
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)          }
+  .dynsym        : { *(.dynsym)                }
+  .dynstr        : { *(.dynstr)                }
+  .rel.text      : { *(.rel.text)              }
+  .rela.text     : { *(.rela.text)     }
+  .rel.data      : { *(.rel.data)              }
+  .rela.data     : { *(.rela.data)     }
+  .rel.rodata    : { *(.rel.rodata)    }
+  .rela.rodata   : { *(.rela.rodata)   }
+  .rel.got       : { *(.rel.got)               }
+  .rela.got      : { *(.rela.got)              }
+  .rel.ctors     : { *(.rel.ctors)     }
+  .rela.ctors    : { *(.rela.ctors)    }
+  .rel.dtors     : { *(.rel.dtors)     }
+  .rela.dtors    : { *(.rela.dtors)    }
+  .rel.bss       : { *(.rel.bss)               }
+  .rela.bss      : { *(.rela.bss)              }
+  .rel.plt       : { *(.rel.plt)               }
+  .rela.plt      : { *(.rela.plt)              }
+  .init          : { *(.init)  }
+  .plt : { *(.plt) }
+  .text      :
+  {
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.eh_frame)
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  } :text
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bootpg ADDR(.text) + 0x7f000 :
+  {
+    cpu/mpc85xx/start.o        (.bootpg)
+  } :text = 0xffff
+
+  .resetvec ADDR(.text) + 0x7fffc :
+  {
+    *(.resetvec)
+  } :text = 0xffff
+
+  . = ADDR(.text) + 0x80000;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/doc/README.p2020rdb b/doc/README.p2020rdb
new file mode 100644 (file)
index 0000000..8a2302f
--- /dev/null
@@ -0,0 +1,145 @@
+Overview
+--------
+P2020RDB is a Low End Dual core platform supporting the P2020 processor
+of QorIQ series. P2020 is an e500 based dual core SOC.
+
+Building U-boot
+-----------
+To build the u-boot for P2020RDB:
+       make P2020RDB_config
+       make
+
+NOR Flash Banks
+-----------
+RDB board for P2020 has two flash banks. They are both present on boot.
+
+Booting by default is always from the boot bank at 0xef00_0000.
+
+Memory Map
+----------
+0xef00_0000 - 0xef7f_ffff      Alernate bank           8MB
+0xe800_0000 - 0xefff_ffff      Boot bank               8MB
+
+0xef78_0000 - 0xef7f_ffff      Alternate u-boot address        512KB
+0xeff8_0000 - 0xefff_ffff      Boot u-boot address             512KB
+
+Switch settings to boot from the NOR flash banks
+------------------------------------------------
+SW4[8]=0 default NOR Flash bank
+SW4[8]=1 Alternate NOR Flash bank
+
+Flashing Images
+---------------
+To place a new u-boot image in the alternate flash bank and then boot
+with that new image temporarily, use this:
+       tftp 1000000 u-boot.bin
+       erase ef780000 ef7fffff
+       cp.b 1000000 ef780000 80000
+
+Now to boot from the alternate bank change the SW4[8] from 0 to 1.
+
+To program the image in the boot flash bank:
+       tftp 1000000 u-boot.bin
+       protect off all
+       erase eff80000 ffffffff
+       cp.b 1000000 eff80000 80000
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+       dtc -b 0 -f -I dts -O dtb p2020rdb.dts > p2020rdb.dtb
+
+Likely, that .dts file will come from here;
+
+       linux-2.6/arch/powerpc/boot/dts/p2020rdb.dts
+
+Booting Linux
+-------------
+Place a linux uImage in the TFTP disk area.
+
+       tftp 1000000 uImage.p2020rdb
+       tftp 2000000 rootfs.ext2.gz.uboot
+       tftp c00000 p2020rdb.dtb
+       bootm 1000000 2000000 c00000
+
+Implementing AMP(Asymmetric MultiProcessing)
+---------------------------------------------
+1. Build kernel image for core0:
+
+       a. $ make 85xx/p1_p2_rdb_defconfig
+
+       b. $ make menuconfig
+          - un-select "Processor support"->
+               "Symetric multi-processing support"
+
+       c. $ make uImage
+
+       d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
+
+2. Build kernel image for core1:
+
+       a. $ make 85xx/p1_p2_rdb_defconfig
+
+       b. $ make menuconfig
+          - Un-select "Processor support"->
+               "Symetric multi-processing support"
+          - Select "Advanced setup" ->
+               "Prompt for advanced kernel configuration options"
+               - Select
+                       "Set physical address where the kernel is loaded"
+                       and set it to 0x20000000, asssuming core1 will
+                       start from 512MB.
+               - Select "Set custom page offset address"
+               - Select "Set custom kernel base address"
+               - Select "Set maximum low memory"
+          - "Exit" and save the selection.
+
+       c. $ make uImage
+
+       d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
+
+3. Create dtb for core0:
+
+       $ dtc -I dts -O dtb -f -b 0
+                arch/powerpc/boot/dts/p2020rdb_camp_core0.dts >
+                /tftpboot/p2020rdb_camp_core0.dtb
+
+4. Create dtb for core1:
+
+       $ dtc -I dts -O dtb -f -b 1
+                arch/powerpc/boot/dts/p2020rdb_camp_core1.dts >
+                /tftpboot/p2020rdb_camp_core1.dtb
+
+5. Bring up two cores separately:
+
+       a. Power on the board, under u-boot prompt:
+               => setenv <serverip>
+               => setenv <ipaddr>
+               => setenv bootargs root=/dev/ram rw console=ttyS0,115200
+       b. Bring up core1's kernel first:
+               => setenv bootm_low 0x20000000
+               => setenv bootm_size 0x10000000
+               => tftp 21000000 uImage.core1
+               => tftp 22000000 ramdiskfile
+               => tftp 20c00000 p2020rdb_camp_core1.dtb
+               => interrupts off
+               => bootm start 21000000 22000000 20c00000
+               => bootm loados
+               => bootm ramdisk
+               => bootm fdt
+               => fdt boardsetup
+               => fdt chosen $initrd_start $initrd_end
+               => bootm prep
+               => cpu 1 release $bootm_low - $fdtaddr -
+       c. Bring up core0's kernel(on the same u-boot console):
+               => setenv bootm_low 0
+               => setenv bootm_size 0x20000000
+               => tftp 1000000 uImage.core0
+               => tftp 2000000 ramdiskfile
+               => tftp c00000 p2020rdb_camp_core0.dtb
+               => bootm 1000000 2000000 c00000
+
+Please note only core0 will run u-boot, core1 starts kernel directly
+after "cpu release" command is issued.
index a5747e10bdef6de5db6dbf5f33efea87718cb25a..db4b1eaa1e919afdbf2861629f973bbd5519c8fd 100644 (file)
@@ -86,7 +86,7 @@ typedef       struct  global_data {
        u32  mem_sec_clk;
 #endif /* CONFIG_MPC8360 */
 #endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8536)
+#if defined(CONFIG_FSL_ESDHC)
        u32 sdhc_clk;
 #endif
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
new file mode 100644 (file)
index 0000000..ff4a5cb
--- /dev/null
@@ -0,0 +1,556 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * P1 P2 RDB board configuration file
+ * This file is intended to address a set of Low End and Ultra Low End
+ * Freescale SOCs of QorIQ series(RDB platforms).
+ * Currently only P2020RDB
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE           1       /* BOOKE */
+#define CONFIG_E500            1       /* BOOKE e500 family */
+#define CONFIG_MPC85xx         1       /* MPC8540/60/55/41/48/P1020/P2020,etc*/
+#define CONFIG_FSL_ELBC                1       /* Enable eLBC Support */
+#define CONFIG_FSL_LAW         1       /* Use common FSL init code */
+#define CONFIG_TSEC_ENET               /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_DDR_CLK_FREQ    66666666 /* DDRCLK on P1_P2 RDB */
+#define CONFIG_SYS_CLK_FREQ    get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
+
+#if defined(CONFIG_P2020) || defined(CONFIG_P1020)
+#define CONFIG_MP
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE                        /* toggle L2 cache */
+#define CONFIG_BTB                     /* toggle branch predition */
+
+#define CONFIG_ADDR_STREAMING          /* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS       1
+
+#define CONFIG_SYS_MEMTEST_START       0x00000000      /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END         0x1fffffff
+#define CONFIG_PANIC_HANG      /* do not reset board on panic */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR             0xffe00000      /* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS        CONFIG_SYS_CCSRBAR      /* physical addr of */
+                                                       /* CCSRBAR */
+#define CONFIG_SYS_IMMR                CONFIG_SYS_CCSRBAR      /* PQII uses */
+                                                       /* CONFIG_SYS_IMMR */
+#define CONFIG_SYS_PCIE2_ADDR          (CONFIG_SYS_CCSRBAR+0x9000)
+#define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_DLL
+
+#define CONFIG_MEM_INIT_VALUE  0xDeadBeef
+
+#define CONFIG_SYS_SDRAM_SIZE  1024    /* DDR size on P1_P2 RDBs */
+#define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
+#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS     1
+#define CONFIG_DIMM_SLOTS_PER_CTLR     1
+#define CONFIG_CHIP_SELECTS_PER_CTRL   1
+
+#define CONFIG_SYS_DDR_ERR_INT_EN      0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS         0x00000000
+#define CONFIG_SYS_DDR_SBE             0x00FF0000
+
+#define CONFIG_SYS_DDR_TLB_START 9
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x3fff_ffff     DDR                     1G cacheablen
+ * 0xa000_0000 0xbfff_ffff     PCI Express Mem         1G non-cacheable
+ * 0xffc2_0000 0xffc5_ffff     PCI IO range            256K non-cacheable
+ *
+ * Localbus cacheable (TBD)
+ * 0xXXXX_XXXX 0xXXXX_XXXX     SRAM                    YZ M Cacheable
+ *
+ * Localbus non-cacheable
+ * 0xef00_0000 0xefff_ffff     FLASH                   16M non-cacheable
+ * 0xffa0_0000 0xffaf_ffff     NAND                    1M non-cacheable
+ * 0xffb0_0000 0xffbf_ffff     VSC7385 switch          1M non-cacheable
+ * 0xffd0_0000 0xffd0_3fff     L1 for stack            16K Cacheable TLB0
+ * 0xffe0_0000 0xffef_ffff     CCSR                    1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE          0xef000000      /* start of FLASH 16M */
+
+#define CONFIG_SYS_FLASH_BASE_PHYS     CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+                                       BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM         0xff000ff7
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT      128     /* sectors per device */
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE        TEXT_BASE       /* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+
+#define CONFIG_BOARD_EARLY_INIT_R      /* call board_early_init_r function */
+
+#define CONFIG_SYS_INIT_RAM_LOCK       1
+#define CONFIG_SYS_INIT_RAM_ADDR      0xffd00000       /* stack in RAM */
+#define CONFIG_SYS_INIT_RAM_END        0x00004000      /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE       128     /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END \
+                                               - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon*/
+#define CONFIG_SYS_MALLOC_LEN          (1024 * 1024)   /* Reserved for malloc*/
+
+#define CONFIG_SYS_NAND_BASE           0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST      {CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define NAND_MAX_CHIPS                 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND                        1
+#define CONFIG_NAND_FSL_ELBC           1
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (16 * 1024)
+
+/* NAND flash config */
+#define CONFIG_NAND_BR_PRELIM  (CONFIG_SYS_NAND_BASE_PHYS \
+                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+                               | BR_PS_8       /* Port Size = 8 bit */ \
+                               | BR_MS_FCM             /* MSEL = FCM */ \
+                               | BR_V)                 /* valid */
+
+#define CONFIG_NAND_OR_PRELIM  (0xFFF80000             /* length 32K */ \
+                               | OR_FCM_CSCT \
+                               | OR_FCM_CST \
+                               | OR_FCM_CHT \
+                               | OR_FCM_SCY_1 \
+                               | OR_FCM_TRLX \
+                               | OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
+
+#define CONFIG_SYS_VSC7385_BASE        0xffb00000
+
+#define CONFIG_SYS_VSC7385_BASE_PHYS   CONFIG_SYS_VSC7385_BASE
+
+#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+                               OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
+                               OR_GPCM_EHTR | OR_GPCM_EAD)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX      1
+//#define CONFIG_CONS_INDEX    2
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK         get_bus_freq(0)
+
+#define CONFIG_SERIAL_MULTI    1 /* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV   /* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE      \
+       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT               1
+#define CONFIG_OF_BOARD_SETUP          1
+#define CONFIG_OF_STDOUT_VIA_ALIAS     1
+
+#define CONFIG_SYS_64BIT_VSPRINTF      1
+#define CONFIG_SYS_64BIT_STRTOUL       1
+
+/* new uImage format support */
+#define CONFIG_FIT             1
+#define CONFIG_FIT_VERBOSE     1 /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C         /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C                /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C         /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED           400000  /* I2C speed and slave address*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_SLAVE           0x7F
+#define CONFIG_SYS_I2C_NOPROBES        {{0,0x29}}      /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET          0x3000
+#define CONFIG_SYS_I2C2_OFFSET         0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM      1
+
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR                0x68
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT       0xffc20000
+#define CONFIG_SYS_PCIE2_IO_BUS        0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS       0xffc20000
+#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
+
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT      0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS       0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT       0xffc30000
+#define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS       0xffc30000
+#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP                 /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#undef CONFIG_RTL8139
+
+#ifdef CONFIG_RTL8139
+/* This macro is used by RTL8139 but not defined in PPC architecture */
+#define KSEG1ADDR(x)           (x)
+#define _IO_BASE       0x00000000
+#endif
+
+
+#define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI       1
+#endif
+
+#define CONFIG_MII             1       /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC        1       /* Allow unregistered phys */
+#define CONFIG_TSEC1   1
+#define CONFIG_TSEC1_NAME      "eTSEC1"
+#define CONFIG_TSEC2   1
+#define CONFIG_TSEC2_NAME      "eTSEC2"
+#define CONFIG_TSEC3   1
+#define CONFIG_TSEC3_NAME      "eTSEC3"
+
+#define TSEC1_PHY_ADDR         2
+#define TSEC2_PHY_ADDR         0
+#define TSEC3_PHY_ADDR         1
+
+#define CONFIG_VSC7385_ENET
+
+#define TSEC1_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX           0
+#define TSEC2_PHYIDX           0
+#define TSEC3_PHYIDX           0
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+/* The size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE_SIZE      8192
+#endif
+
+#define CONFIG_ETHPRIME                "eTSEC1"
+
+#define CONFIG_PHY_GIGE                1       /* Include GbE speed/duplex detection */
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR                0xfff80000
+#else
+#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SIZE                0x2000
+#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
+
+#define CONFIG_LOADS_ECHO      1       /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#endif
+
+#undef CONFIG_WATCHDOG                 /* watchdog disabled */
+
+#define CONFIG_MMC     1
+
+#ifdef CONFIG_MMC
+#define CONFIG_BOARD_EARLY_INIT_F      1       /* Call board_pre_init */
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FSL_ESDHC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#ifdef CONFIG_P2020
+#define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
+#endif
+#endif
+
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING                 /* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
+#define CONFIG_SYS_PROMPT      "=> "           /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+                                               /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS     16              /* max number of command args */
+#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ          1000            /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ   (16 << 20)/* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM  0x02            /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE   230400  /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX  2       /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#endif
+
+#define CONFIG_HOSTNAME                P2020RDB
+#define CONFIG_ROOTPATH                /opt/nfsroot
+#define CONFIG_BOOTFILE                uImage
+#define CONFIG_UBOOTPATH       u-boot.bin/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR                1000000
+
+#define CONFIG_BOOTDELAY 10    /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS                /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE        115200
+
+#define        CONFIG_EXTRA_ENV_SETTINGS                               \
+       "netdev=eth0\0"                                         \
+       "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
+       "loadaddr=1000000\0"                    \
+       "bootfile=uImage\0"     \
+       "tftpflash=tftpboot $loadaddr $uboot; "                 \
+               "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
+               "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
+               "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
+               "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
+               "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
+       "consoledev=ttyS0\0"                            \
+       "ramdiskaddr=2000000\0"                 \
+       "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
+       "fdtaddr=c00000\0"                              \
+       "fdtfile=p2020rdb.dtb\0"                \
+       "bdev=sda1\0"   \
+       "jffs2nor=mtdblock3\0"  \
+       "norbootaddr=ef080000\0"        \
+       "norfdtaddr=ef040000\0" \
+       "jffs2nand=mtdblock9\0" \
+       "nandbootaddr=100000\0" \
+       "nandfdtaddr=80000\0"           \
+       "nandimgsize=400000\0"          \
+       "nandfdtsize=80000\0"           \
+       "usb_phy_type=ulpi\0"           \
+       "vscfw_addr=ef000000\0" \
+       "othbootargs=ramdisk_size=600000\0" \
+       "usbfatboot=setenv bootargs root=/dev/ram rw "  \
+       "console=$consoledev,$baudrate $othbootargs; "  \
+       "usb start;"                    \
+       "fatload usb 0:2 $loadaddr $bootfile;"          \
+       "fatload usb 0:2 $fdtaddr $fdtfile;"    \
+       "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
+       "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
+       "usbext2boot=setenv bootargs root=/dev/ram rw " \
+       "console=$consoledev,$baudrate $othbootargs; "  \
+       "usb start;"                    \
+       "ext2load usb 0:4 $loadaddr $bootfile;"         \
+       "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
+       "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
+       "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
+       "norboot=setenv bootargs root=/dev/$jffs2nor rw "       \
+       "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
+       "bootm $norbootaddr - $norfdtaddr\0"            \
+       "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
+       "console=$consoledev,$baudrate $othbootargs;"   \
+       "nand read 2000000 $nandbootaddr $nandimgsize;" \
+       "nand read 3000000 $nandfdtaddr $nandfdtsize;"  \
+       "bootm 2000000 - 3000000;\0"
+
+#define CONFIG_NFSBOOTCOMMAND          \
+       "setenv bootargs root=/dev/nfs rw "     \
+       "nfsroot=$serverip:$rootpath "          \
+       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+       "console=$consoledev,$baudrate $othbootargs;"   \
+       "tftp $loadaddr $bootfile;"             \
+       "tftp $fdtaddr $fdtfile;"               \
+       "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_HDBOOT                  \
+       "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
+       "console=$consoledev,$baudrate $othbootargs;"   \
+       "usb start;"                    \
+       "ext2load usb 0:1 $loadaddr /boot/$bootfile;"           \
+       "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
+       "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND          \
+       "setenv bootargs root=/dev/ram rw "     \
+       "console=$consoledev,$baudrate $othbootargs; "  \
+       "tftp $ramdiskaddr $ramdiskfile;"       \
+       "tftp $loadaddr $bootfile;"             \
+       "tftp $fdtaddr $fdtfile;"               \
+       "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND             CONFIG_HDBOOT
+
+#endif /* __CONFIG_H */