mips: bmips: add bcm63xx-hsspi driver support for BCM63268

This driver manages the high speed SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi
index 6e3d9c3820ff197fb6841a0339d1a1a364b5b9e2..4d4e36ccccf27a9f158c7e2c9ea941ef6bd85bc2 100644 (file)
--- a/arch/mips/dts/brcm,bcm63268.dtsi
+++ b/arch/mips/dts/brcm,bcm63268.dtsi
@@ -15,6 +15,7 @@
 
        aliases {
                spi0 = &lsspi;
+               spi1 = &hsspi;
        };
 
        cpus {
@@ -44,6 +45,12 @@
                #size-cells = <1>;
                u-boot,dm-pre-reloc;
 
+               hsspi_pll: hsspi-pll {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <400000000>;
+               };
+
                periph_osc: periph-osc {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
@@ -153,6 +160,20 @@
                        status = "disabled";
                };
 
+               hsspi: spi@10001000 {
+                       compatible = "brcm,bcm6328-hsspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x10001000 0x600>;
+                       clocks = <&periph_clk BCM63268_CLK_HSSPI>, <&hsspi_pll>;
+                       clock-names = "hsspi", "pll";
+                       resets = <&periph_rst BCM63268_RST_SPI>;
+                       spi-max-frequency = <50000000>;
+                       num-cs = <8>;
+
+                       status = "disabled";
+               };
+
                leds: led-controller@10001900 {
                        compatible = "brcm,bcm6328-leds";
                        reg = <0x10001900 0x24>;