Merge with /home/sr/git/u-boot/cfi-flash

diff --combined CHANGELOG
index 59f12b8afb3c11fdd504ce93ffa65584a5b7d6cf,4c5b62c068947bde73e265526fb2900df215e55f..5040a6b1dbbcf4e10d81216f1a00b15d34ec5ee9
--- 1/CHANGELOG
--- 2/CHANGELOG
+++ b/CHANGELOG
@@@ -2,46 -2,33 +2,73 @@@
  Changes since U-Boot 1.1.4:
  ======================================================================
  
+ * Changes/fixes for drivers/cfi_flash.c:
+ 
+   - Add Intel legacy lock/unlock support to common CFI driver
+ 
+     On some Intel flash's (e.g. Intel J3) legacy unlocking is
+     supported, meaning that unlocking of one sector will unlock
+     all sectors of this bank. Using this feature, unlocking
+     of all sectors upon startup (via env var "unlock=yes") will
+     get much faster.
+ 
+   - Fixed problem with multiple reads of envronment variable
+     "unlock" as pointed out by Reinhard Arlt & Anders Larsen.
+ 
+   - Removed unwanted linefeeds from "protect" command when
+     CFG_FLASH_PROTECTION is enabled.
+ 
+   - Changed p3p400 board to use CFG_FLASH_PROTECTION
+ 
+   Patch by Stefan Roese, 01 Apr 2006
+ 
+ * Changes/fixes for drivers/cfi_flash.c:
+   - Correctly handle the cases where CFG_HZ != 1000 (several
+     XScale-based boards)
+   - Fix the timeout calculation of buffered writes (off by a
+     factor of 1000)
+   Patch by Anders Larsen, 31 Mar 2006
+ 
 +* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)
 +
 +  405 SDRAM: - The SDRAM parameters can now be defined in the board
 +               config file and the 405 SDRAM controller values will
 +               be calculated upon bootup (see PPChameleonEVB).
 +               When those settings are not defined in the board
 +               config file, the register setup will be as it is now,
 +               so this implementation should not break any current
 +               design using this code.
 +
 +               Thanks to Andrea Marson from DAVE for this patch.
 +
 +  440 DDR:   - Added function sdram_tr1_set to auto calculate the
 +               TR1 value for the DDR.
 +             - Added ECC support (see p3p440).
 +
 +  Patch by Stefan Roese, 17 Mar 2006
 +
 +* Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.S
 +  Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473]
 +
 +* Add support for ymodem protocol download
 +  Patch by Stefano Babic, 29 Mar 2006
 +
 +* Memory Map Update for Delta board: U-Boot is at 0x80000000-0x84000000
 +  Merge from Markus Klotzbücher's repo, 01 Apr 2006
 +
 +* GCC-4.x fixes: clean up global data pointer initialization for all
 +  boards
 +
 +* Update for Delta board:
 +  - redundant NAND environment
 +  - misc Monahans cleanups (remove dead code etc.)
 +  - DA9030 Initialization; some minimal changes to PXA I2C driver to
 +    make it work with the Monahans.
 +  - Make Monahans clock frequency configurable using
 +    CFG_MONAHANS_RUN_MODE_OSC_RATIO and
 +    CFG_MONAHANS_TURBO_RUN_MODE_RATIO.
 +  Merge from Markus Klotzbücher's repo, 25 Mar 2006
 +
  * Enable Quad UART om MCC200 board.
  
  * Cleanup MCC200 board configuration; omit non-existent stuff.

diff --combined include/configs/p3p440.h
index 0662544aed27b0c62c23f4d8eda4d765d2e9eeeb,19656fc22af3787e633859a41ac98a554e96cb89..aa0901f3ff467d8a04d7844485a681e348b0c0fe
--- 1/include/configs/p3p440.h
--- 2/include/configs/p3p440.h
+++ b/include/configs/p3p440.h
@@@ -1,5 -1,5 +1,5 @@@
  /*
 - * (C) Copyright 2005
 + * (C) Copyright 2005-2006
   * Stefan Roese, DENX Software Engineering, sr@denx.de.
   *
   * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
@@@ -71,10 -71,9 +71,10 @@@
   * DDR SDRAM
   *----------------------------------------------------------------------*/
  #define CONFIG_SDRAM_BANK0    1       /* init onboard DDR SDRAM bank 0*/
 -#define CFG_SDRAM_TABLE       {       \
 -              {(256 << 20), 0x000C4001}, /* 256MB mode 3, 13x10(4) */ \
 -              {(64 << 20),  0x00082001}} /* 64MB mode 2, 12x9(4)   */
 +#define CONFIG_SDRAM_ECC              /* enable ECC support           */
 +#define CFG_SDRAM_TABLE       { \
 +              {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
 +              {(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)  */
  
  /*-----------------------------------------------------------------------
   * Serial Port
@@@ -147,6 -146,7 +147,7 @@@
                "cp.b 100000 fffc0000 40000;"                           \
                "setenv filesize;saveenv\0"                             \
        "upd=run load;run update\0"                                     \
+       "unlock=yes\0"                                                  \
        ""
  #define CONFIG_BOOTCOMMAND    "run net_nfs"
  
@@@ -276,8 -276,8 +277,8 @@@
  #define CFG_FLASH_ERASE_TOUT  120000  /* Timeout for Flash Erase (in ms)      */
  #define CFG_FLASH_WRITE_TOUT  500     /* Timeout for Flash Write (in ms)      */
  
 -#define CFG_FLASH_PROTECTION  1          /* use hardware protection           */
 -#define CFG_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)  */
 +#define CFG_FLASH_USE_BUFFER_WRITE 1  /* use buffered writes (20x faster)     */
- #define CFG_FLASH_PROTECTION  1       /* hardware flash protection            */
++#define CFG_FLASH_PROTECTION  1       /* use hardware flash protection        */
  
  #define CFG_FLASH_EMPTY_INFO          /* print 'E' for empty sector on flinfo */
  #define CFG_FLASH_QUIET_TEST  1       /* don't warn upon unknown flash        */