ColdFire: Update for M54451EVB

Update serial boot DRAM's Internal RAM, vector table and DRAM in
start.S, serial flash's read status command over SPI and NOR
flash.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>

diff --git a/Makefile b/Makefile
index 090e64522b456efa9c04ad132e1b27e71746968a..03148445ccfce018357d8d1286b7ab4a7b62f92b 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -2108,18 +2108,15 @@ M5373EVB_config :       unconfig
        @$(MKCONFIG) -a M5373EVB m68k mcf532x m5373evb freescale
 
 M54451EVB_config \
-M54451EVB_spansion_config \
 M54451EVB_stmicro_config :     unconfig
        @case "$@" in \
-       M54451EVB_config)               FLASH=SPANSION;; \
-       M54451EVB_spansion_config)      FLASH=SPANSION;; \
+       M54451EVB_config)               FLASH=NOR;; \
        M54451EVB_stmicro_config)       FLASH=STMICRO;; \
        esac; \
-       if [ "$${FLASH}" = "SPANSION" ] ; then \
-               echo "#define CONFIG_SYS_SPANSION_BOOT" >> $(obj)include/config.h ; \
+       if [ "$${FLASH}" = "NOR" ] ; then \
                echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54451evb/config.tmp ; \
                cp $(obj)board/freescale/m54451evb/u-boot.spa $(obj)board/freescale/m54451evb/u-boot.lds ; \
-               $(XECHO) "... with SPANSION boot..." ; \
+               $(XECHO) "... with NOR boot..." ; \
        fi; \
        if [ "$${FLASH}" = "STMICRO" ] ; then \
                echo "#define CONFIG_CF_SBF"    >> $(obj)include/config.h ; \

diff --git a/board/freescale/m54451evb/u-boot.spa b/board/freescale/m54451evb/u-boot.spa
index 08e184c1e66cbcdffa69ae0ee43f274bf22d0c4c..d8caefad6498fba33a17d8e43aa9da862f167819 100644 (file)
--- a/board/freescale/m54451evb/u-boot.spa
+++ b/board/freescale/m54451evb/u-boot.spa
@@ -56,10 +56,13 @@ SECTIONS
     /* the sector layout of our flash chips!   XXX FIXME XXX   */
 
     cpu/mcf5445x/start.o               (.text)
-    lib_m68k/traps.o           (.text)
-    lib_m68k/interrupts.o      (.text)
+    cpu/mcf5445x/libmcf5445x.a (.text)
+    lib_m68k/libm68k.a         (.text)
+    common/cmd_flash.o         (.text)
     common/dlmalloc.o          (.text)
-    lib_generic/zlib.o         (.text)
+    common/main.o              (.text)
+    common/image.o             (.text)
+    lib_generic/libgeneric.a   (.text)
 
     . = DEFINED(env_offset) ? env_offset : .;
     common/env_embedded.o      (.text)

diff --git a/cpu/mcf5445x/dspi.c b/cpu/mcf5445x/dspi.c
index 6d3ebab6ef90168c6f67734efbc9509681d38e69..59133e84d8d5ca02728b5347bf4d33c9bf888b30 100644 (file)
--- a/cpu/mcf5445x/dspi.c
+++ b/cpu/mcf5445x/dspi.c
@@ -159,12 +159,10 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
                        dspi_rx();
                        return 0;
                case 0x05:      /* Read Status */
-                       if (len == 4)
-                               if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
-                                   && (spi_wr[3] == 0xFF)) {
-                                       dspi_tx(slave->cs, 0x80, *spi_wr);
-                                       dspi_rx();
-                               }
+                       if (len == 1) {
+                               dspi_tx(slave->cs, 0x80, *spi_wr);
+                               dspi_rx();
+                       }
                        return 0;
                case 0x06:      /* WREN */
                        dspi_tx(slave->cs, 0x00, *spi_wr);

diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S
index 26fb2ce0cbd8933407fb19830358fe83eadf5c98..c156bab037fa8d8a72738601de2721db50a385d2 100644 (file)
--- a/cpu/mcf5445x/start.S
+++ b/cpu/mcf5445x/start.S
@@ -149,9 +149,35 @@ asm_sbf_img_hdr:
        .long   0x00030000      /* image length */
        .long   TEXT_BASE       /* image to be relocated at */
 
+
+
 asm_dram_init:
+       move.w #0x2700,%sr              /* Mask off Interrupt */
+
+       move.l  #CONFIG_SYS_INIT_RAM_ADDR, %d0
+       movec   %d0, %VBR
+
        move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
-       movec   %d0, %RAMBAR1   /* init Rambar */
+       movec   %d0, %RAMBAR1
+
+       /* initialize general use internal ram */
+       move.l #0, %d0
+       move.l #(CACR_STATUS), %a1      /* CACR */
+       move.l #(ICACHE_STATUS), %a2    /* icache */
+       move.l #(DCACHE_STATUS), %a3    /* dcache */
+       move.l %d0, (%a1)
+       move.l %d0, (%a2)
+       move.l %d0, (%a3)
+
+       /* invalidate and disable cache */
+       move.l  #0x01004100, %d0        /* Invalidate cache cmd */
+       movec   %d0, %CACR              /* Invalidate cache */
+       move.l  #0, %d0
+       movec   %d0, %ACR0
+       movec   %d0, %ACR1
+       movec   %d0, %ACR2
+       movec   %d0, %ACR3
+
        move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
        clr.l %sp@-
 
@@ -163,10 +189,7 @@ asm_dram_init:
        move.l  #0xFC008004, %a1
        move.l  #(CONFIG_SYS_CS0_MASK), (%a1)
 
-       /*
-        * Dram Initialization
-        * a1, a2, and d0
-        */
+       /* Dram Initialization a1, a2, and d0 */
        /* mscr sdram */
        move.l  #0xFC0A4074, %a1
        move.b  #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
@@ -209,24 +232,21 @@ dramsz_loop:
        move.l  #0xFC0B8000, %a1        /* Mode */
        move.l  #0xFC0B8004, %a2        /* Ctrl */
 
-#ifdef CONFIG_M54455EVB
        /* Issue PALL */
        move.l  #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
        nop
 
+#ifdef CONFIG_M54455EVB
        /* Issue LEMR */
        move.l  #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
        nop
        move.l  #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
        nop
-
-       move.l  #1000, %d0
-wait1000:
-       nop
-       subq.l  #1, %d0
-       bne     wait1000
 #endif
 
+       move.l  #1000, %d1
+       jsr     asm_delay
+
        /* Issue PALL */
        move.l  #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
        nop
@@ -246,25 +266,24 @@ wait1000:
        move.l  #(CONFIG_SYS_SDRAM_MODE), (%a1)
        nop
        move.l  #(CONFIG_SYS_SDRAM_EMOD), (%a1)
-       nop
 #endif
 
-       move.l  #500, %d0
-wait500:
-       nop
-       subq.l  #1, %d0
-       bne     wait500
+       move.l  #500, %d1
+       jsr     asm_delay
 
-       move.l  #(CONFIG_SYS_SDRAM_CTRL), %d0
-       and.l   #0x7FFFFFFF, %d0
+       move.l  #(CONFIG_SYS_SDRAM_CTRL), %d1
+       and.l   #0x7FFFFFFF, %d1
 #ifdef CONFIG_M54455EVB
-       or.l    #0x10000c00, %d0
+       or.l    #0x10000C00, %d1
 #elif defined(CONFIG_M54451EVB)
-       or.l    #0x10000000, %d0
+       or.l    #0x10000C00, %d1
 #endif
-       move.l  %d0, (%a2)
+       move.l  %d1, (%a2)
        nop
 
+       move.l  #2000, %d1
+       jsr     asm_delay
+
        /*
         * DSPI Initialization
         * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
@@ -274,6 +293,7 @@ wait500:
         * a4 - Dst addr
         */
        /* Enable pins for DSPI mode - chip-selects are enabled later */
+asm_dspi_init:
        move.l  #0xFC0A4063, %a0
        move.b  #0x7F, (%a0)
 
@@ -367,27 +387,29 @@ asm_dspi_rd_status:
 
        move.b  (%a3), %d1
        rts
+
+asm_delay:
+       nop
+       subq.l  #1, %d1
+       bne     asm_delay
+       rts
 #endif                 /* CONFIG_CF_SBF */
 
        .text
        . = 0x400
        .globl  _start
 _start:
+#if !defined(CONFIG_CF_SBF)
        nop
        nop
        move.w #0x2700,%sr              /* Mask off Interrupt */
 
        /* Set vector base register at the beginning of the Flash */
-#if defined(CONFIG_CF_SBF)
-       move.l  #TEXT_BASE, %d0
-       movec   %d0, %VBR
-#else
        move.l  #CONFIG_SYS_FLASH_BASE, %d0
        movec   %d0, %VBR
 
        move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
        movec   %d0, %RAMBAR1
-#endif
 
        /* initialize general use internal ram */
        move.l #0, %d0
@@ -411,6 +433,7 @@ _start:
           the first c-code */
        move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
        clr.l %sp@-
+#endif
 
        move.l #__got_start, %a5        /* put relocation table address to a5 */
 
@@ -532,7 +555,7 @@ icache_enable:
        move.l  #0x00040100, %d0        /* Invalidate icache */
        movec   %d0, %CACR
 
-       move.l  #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 /* Setup icache */
+       move.l  #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0  /* Setup icache */
        movec   %d0, %ACR2
 
        move.l  #0x04088020, %d0        /* Enable bcache and icache */

diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 45f701652f16377efa1d5a47292d171302724da3..cc57da816bba3070413770a1d294499153c24beb 100644 (file)
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -70,6 +70,7 @@
 #define CONFIG_CMD_MISC
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SPI
@@ -163,7 +164,7 @@
 #define CONFIG_SYS_I2C_SPEED           80000   /* I2C speed and slave address  */
 #define CONFIG_SYS_I2C_SLAVE           0x7F
 #define CONFIG_SYS_I2C_OFFSET          0x58000
-#define CONFIG_SYS_IMMR                CONFIG_SYS_MBAR
+#define CONFIG_SYS_IMMR                        CONFIG_SYS_MBAR
 
 /* DSPI and Serial Flash */
 #define CONFIG_CF_DSPI
@@ -175,7 +176,7 @@
 #      define CONFIG_SPI_FLASH
 #      define CONFIG_SPI_FLASH_STMICRO
 
-#      define CONFIG_SYS_DSPI_DCTAR0           (DSPI_DCTAR_TRSZ(7) | \
+#      define CONFIG_SYS_DSPI_DCTAR0   (DSPI_DCTAR_TRSZ(7) | \
                                         DSPI_DCTAR_CPOL | \
                                         DSPI_DCTAR_CPHA | \
                                         DSPI_DCTAR_PCSSCK_1CLK | \
@@ -191,7 +192,7 @@
 /* Input, PCI, Flexbus, and VCO */
 #define CONFIG_EXTRA_CLOCK
 
-#define CONFIG_PRAM            2048    /* 2048 KB */
+#define CONFIG_PRAM                    2048    /* 2048 KB */
 
 #define CONFIG_SYS_PROMPT              "-> "
 #define CONFIG_SYS_LONGHELP            /* undef to save memory */
@@ -209,7 +210,7 @@
 
 #define CONFIG_SYS_HZ                  1000
 
-#define CONFIG_SYS_MBAR                0xFC000000
+#define CONFIG_SYS_MBAR                        0xFC000000
 
 /*
  * Low Level Configuration Settings
@@ -265,7 +266,7 @@
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
  */
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SYS_STMICRO_BOOT)
 #      define CONFIG_ENV_IS_IN_SPI_FLASH       1
 #      define CONFIG_ENV_SPI_CS                1
 #      define CONFIG_ENV_OFFSET                0x20000
@@ -273,8 +274,9 @@
 #      define CONFIG_ENV_SECT_SIZE     0x10000
 #else
 #      define CONFIG_ENV_IS_IN_FLASH   1
-#      define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x4000)
-#      define CONFIG_ENV_SECT_SIZE     0x2000
+#      define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x8000)
+#      define CONFIG_ENV_SIZE          0x2000
+#      define CONFIG_ENV_SECT_SIZE     0x8000
 #endif
 #undef CONFIG_ENV_OVERWRITE
 #undef CONFIG_ENV_IS_EMBEDDED
@@ -286,8 +288,7 @@
 #      define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_SER_FLASH_BASE
 #      define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_SER_FLASH_BASE
 #      define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS0_BASE
-#endif
-#ifdef CONFIG_SYS_SPANSION_BOOT
+#else
 #      define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 #      define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 #      define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_SER_FLASH_BASE
@@ -297,6 +298,7 @@
 #ifdef CONFIG_SYS_FLASH_CFI
 
 #      define CONFIG_FLASH_CFI_DRIVER  1
+#      define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 #      define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 #      define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 #      define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
@@ -311,27 +313,20 @@
  * This is setting for JFFS2 support in u-boot.
  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
  */
-#ifdef CONFIG_SYS_SPANSION_BOOT
-#      define CONFIG_JFFS2_DEV         "nor0"
-#      define CONFIG_JFFS2_PART_SIZE   0x01000000
-#      define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
-#endif
-#ifdef CONFIG_SYS_STMICRO_BOOT
+#ifdef CONFIG_CMD_JFFS2
 #      define CONFIG_JFFS2_DEV         "nor0"
 #      define CONFIG_JFFS2_PART_SIZE   0x01000000
 #      define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
 #endif
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
+/* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE              16
 
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
 /*
- * CS0 - NOR Flash 8MB
+ * CS0 - NOR Flash 16MB
  * CS1 - Available
  * CS2 - Available
  * CS3 - Available
@@ -339,10 +334,10 @@
  * CS5 - Available
  */
 
- /* SPANSION Flash */
+ /* Flash */
 #define CONFIG_SYS_CS0_BASE            0x00000000
-#define CONFIG_SYS_CS0_MASK            0x007F0001
-#define CONFIG_SYS_CS0_CTRL            0x00001180
+#define CONFIG_SYS_CS0_MASK            0x00FF0001
+#define CONFIG_SYS_CS0_CTRL            0x00004D80
 
 #define CONFIG_SYS_SPANSION_BASE       CONFIG_SYS_CS0_BASE