arm: socfpga: is1: Adding handoff for SDRAM ctrlcfg.extratime1
authorChin Liang See <clsee@altera.com>
Wed, 21 Sep 2016 02:26:00 +0000 (10:26 +0800)
committerMarek Vasut <marex@denx.de>
Thu, 27 Oct 2016 06:03:10 +0000 (08:03 +0200)
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
board/is1/qts/sdram_config.h

index 67ea1ec21e7018873b9709f75afa7dc00553f72a..8ce3c70e78efc6c78309163be8c133f0fdfb9aaf 100644 (file)
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0x777