sunxi: add support for Allwinner H6 SoC
authorIcenowy Zheng <icenowy@aosc.io>
Sat, 21 Jul 2018 08:20:31 +0000 (16:20 +0800)
committerJagan Teki <jagan@amarulasolutions.com>
Tue, 31 Jul 2018 06:08:13 +0000 (11:38 +0530)
Allwinner H6 is a new SoC from Allwinner features USB3 and PCIe
interfaces.

This patch adds support for it.

The corresponding DTSI file, from Linux next-20180720, is also
introduced.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
arch/arm/dts/sun50i-h6.dtsi [new file with mode: 0644]
arch/arm/mach-sunxi/Kconfig
arch/arm/mach-sunxi/cpu_info.c
common/spl/Kconfig
include/dt-bindings/clock/sun50i-h6-ccu.h [new file with mode: 0644]
include/dt-bindings/clock/sun50i-h6-r-ccu.h [new file with mode: 0644]
include/dt-bindings/reset/sun50i-h6-ccu.h [new file with mode: 0644]
include/dt-bindings/reset/sun50i-h6-r-ccu.h [new file with mode: 0644]

diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi
new file mode 100644 (file)
index 0000000..cfa5fff
--- /dev/null
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun50i-h6-ccu.h>
+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
+
+/ {
+       interrupt-parent = <&gic>;
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       device_type = "cpu";
+                       reg = <0>;
+                       enable-method = "psci";
+               };
+
+               cpu1: cpu@1 {
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       device_type = "cpu";
+                       reg = <1>;
+                       enable-method = "psci";
+               };
+
+               cpu2: cpu@2 {
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       device_type = "cpu";
+                       reg = <2>;
+                       enable-method = "psci";
+               };
+
+               cpu3: cpu@3 {
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       device_type = "cpu";
+                       reg = <3>;
+                       enable-method = "psci";
+               };
+       };
+
+       iosc: internal-osc-clk {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <16000000>;
+               clock-accuracy = <300000000>;
+               clock-output-names = "iosc";
+       };
+
+       osc24M: osc24M_clk {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <24000000>;
+               clock-output-names = "osc24M";
+       };
+
+       osc32k: osc32k_clk {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <32768>;
+               clock-output-names = "osc32k";
+       };
+
+       psci {
+               compatible = "arm,psci-0.2";
+               method = "smc";
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                            <GIC_PPI 14
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                            <GIC_PPI 11
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                            <GIC_PPI 10
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               ccu: clock@3001000 {
+                       compatible = "allwinner,sun50i-h6-ccu";
+                       reg = <0x03001000 0x1000>;
+                       clocks = <&osc24M>, <&osc32k>, <&iosc>;
+                       clock-names = "hosc", "losc", "iosc";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               gic: interrupt-controller@3021000 {
+                       compatible = "arm,gic-400";
+                       reg = <0x03021000 0x1000>,
+                             <0x03022000 0x2000>,
+                             <0x03024000 0x2000>,
+                             <0x03026000 0x2000>;
+                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                       interrupt-controller;
+                       #interrupt-cells = <3>;
+               };
+
+               pio: pinctrl@300b000 {
+                       compatible = "allwinner,sun50i-h6-pinctrl";
+                       reg = <0x0300b000 0x400>;
+                       interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
+                       clock-names = "apb", "hosc", "losc";
+                       gpio-controller;
+                       #gpio-cells = <3>;
+                       interrupt-controller;
+                       #interrupt-cells = <3>;
+
+                       mmc0_pins: mmc0-pins {
+                               pins = "PF0", "PF1", "PF2", "PF3",
+                                      "PF4", "PF5";
+                               function = "mmc0";
+                               drive-strength = <30>;
+                               bias-pull-up;
+                       };
+
+                       mmc2_pins: mmc2-pins {
+                               pins = "PC1", "PC4", "PC5", "PC6",
+                                      "PC7", "PC8", "PC9", "PC10",
+                                      "PC11", "PC12", "PC13", "PC14";
+                               function = "mmc2";
+                               drive-strength = <30>;
+                               bias-pull-up;
+                       };
+
+                       uart0_ph_pins: uart0-ph {
+                               pins = "PH0", "PH1";
+                               function = "uart0";
+                       };
+               };
+
+               mmc0: mmc@4020000 {
+                       compatible = "allwinner,sun50i-h6-mmc",
+                                    "allwinner,sun50i-a64-mmc";
+                       reg = <0x04020000 0x1000>;
+                       clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+                       clock-names = "ahb", "mmc";
+                       resets = <&ccu RST_BUS_MMC0>;
+                       reset-names = "ahb";
+                       interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mmc1: mmc@4021000 {
+                       compatible = "allwinner,sun50i-h6-mmc",
+                                    "allwinner,sun50i-a64-mmc";
+                       reg = <0x04021000 0x1000>;
+                       clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+                       clock-names = "ahb", "mmc";
+                       resets = <&ccu RST_BUS_MMC1>;
+                       reset-names = "ahb";
+                       interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mmc2: mmc@4022000 {
+                       compatible = "allwinner,sun50i-h6-emmc",
+                                    "allwinner,sun50i-a64-emmc";
+                       reg = <0x04022000 0x1000>;
+                       clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+                       clock-names = "ahb", "mmc";
+                       resets = <&ccu RST_BUS_MMC2>;
+                       reset-names = "ahb";
+                       interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               uart0: serial@5000000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x05000000 0x400>;
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&ccu CLK_BUS_UART0>;
+                       resets = <&ccu RST_BUS_UART0>;
+                       status = "disabled";
+               };
+
+               uart1: serial@5000400 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x05000400 0x400>;
+                       interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&ccu CLK_BUS_UART1>;
+                       resets = <&ccu RST_BUS_UART1>;
+                       status = "disabled";
+               };
+
+               uart2: serial@5000800 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x05000800 0x400>;
+                       interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&ccu CLK_BUS_UART2>;
+                       resets = <&ccu RST_BUS_UART2>;
+                       status = "disabled";
+               };
+
+               uart3: serial@5000c00 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x05000c00 0x400>;
+                       interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&ccu CLK_BUS_UART3>;
+                       resets = <&ccu RST_BUS_UART3>;
+                       status = "disabled";
+               };
+
+               r_ccu: clock@7010000 {
+                       compatible = "allwinner,sun50i-h6-r-ccu";
+                       reg = <0x07010000 0x400>;
+                       clocks = <&osc24M>, <&osc32k>, <&iosc>,
+                                <&ccu CLK_PLL_PERIPH0>;
+                       clock-names = "hosc", "losc", "iosc", "pll-periph";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               r_intc: interrupt-controller@7021000 {
+                       compatible = "allwinner,sun50i-h6-r-intc",
+                                    "allwinner,sun6i-a31-r-intc";
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       reg = <0x07021000 0x400>;
+                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               r_pio: pinctrl@7022000 {
+                       compatible = "allwinner,sun50i-h6-r-pinctrl";
+                       reg = <0x07022000 0x400>;
+                       interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
+                       clock-names = "apb", "hosc", "losc";
+                       gpio-controller;
+                       #gpio-cells = <3>;
+                       interrupt-controller;
+                       #interrupt-cells = <3>;
+
+                       r_i2c_pins: r-i2c {
+                               pins = "PL0", "PL1";
+                               function = "s_i2c";
+                       };
+               };
+
+               r_i2c: i2c@7081400 {
+                       compatible = "allwinner,sun6i-a31-i2c";
+                       reg = <0x07081400 0x400>;
+                       interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&r_ccu CLK_R_APB2_I2C>;
+                       resets = <&r_ccu RST_R_APB2_I2C>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&r_i2c_pins>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+       };
+};
index 32a46797e26d12ce6924f604d21e856274424a8c..558363b52d23b235a6bdafcaea96612009fc3c95 100644 (file)
@@ -82,6 +82,7 @@ config SUN8I_RSB
 config SUNXI_SRAM_ADDRESS
        hex
        default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
+       default 0x20000 if MACH_SUN50I_H6
        default 0x0
        ---help---
        Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
@@ -287,6 +288,14 @@ config MACH_SUN50I_H5
        select FIT
        select SPL_LOAD_FIT
 
+config MACH_SUN50I_H6
+       bool "sun50i (Allwinner H6)"
+       select ARM64
+       select SUPPORT_SPL
+       select FIT
+       select SPL_LOAD_FIT
+       select DRAM_SUN50I_H6
+
 endchoice
 
 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
@@ -380,6 +389,7 @@ config DRAM_CLK
        default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
                       MACH_SUN8I_V3S
        default 672 if MACH_SUN50I
+       default 744 if MACH_SUN50I_H6
        ---help---
        Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
        must be a multiple of 24. For the sun9i (A80), the tested values
@@ -399,7 +409,7 @@ config DRAM_ZQ
        default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
        default 127 if MACH_SUN7I
        default 14779 if MACH_SUN8I_V3S
-       default 3881979 if MACH_SUN8I_R40
+       default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6
        default 4145117 if MACH_SUN9I
        default 3881915 if MACH_SUN50I
        ---help---
@@ -411,6 +421,7 @@ config DRAM_ODT_EN
        default y if MACH_SUN8I_A23
        default y if MACH_SUN8I_R40
        default y if MACH_SUN50I
+       default y if MACH_SUN50I_H6
        ---help---
        Select this to enable dram odt (on die termination).
 
@@ -501,6 +512,7 @@ config SYS_CLK_FREQ
        default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
        default 1008000000 if MACH_SUN8I
        default 1008000000 if MACH_SUN9I
+       default 888000000 if MACH_SUN50I_H6
 
 config SYS_CONFIG_NAME
        default "sun4i" if MACH_SUN4I
@@ -510,6 +522,7 @@ config SYS_CONFIG_NAME
        default "sun8i" if MACH_SUN8I
        default "sun9i" if MACH_SUN9I
        default "sun50i" if MACH_SUN50I
+       default "sun50i" if MACH_SUN50I_H6
 
 config SYS_BOARD
        default "sunxi"
@@ -715,6 +728,7 @@ config VIDEO_SUNXI
        depends on !MACH_SUN8I_V3S
        depends on !MACH_SUN9I
        depends on !MACH_SUN50I
+       depends on !MACH_SUN50I_H6
        select VIDEO
        imply VIDEO_DT_SIMPLEFB
        default y
@@ -947,6 +961,7 @@ config SPL_STACK_R_ADDR
        default 0x4fe00000 if MACH_SUN8I
        default 0x2fe00000 if MACH_SUN9I
        default 0x4fe00000 if MACH_SUN50I
+       default 0x4fe00000 if MACH_SUN50I_H6
 
 config SPL_SPI_SUNXI
        bool "Support for SPI Flash on Allwinner SoCs in SPL"
index aadf575ef2b05435a5f082eec5fbdec87b352cf3..ae4745bfeccaab0815bd4fc05b60d4526e616bb0 100644 (file)
@@ -96,6 +96,8 @@ int print_cpuinfo(void)
        puts("CPU:   Allwinner A64 (SUN50I)\n");
 #elif defined CONFIG_MACH_SUN50I_H5
        puts("CPU:   Allwinner H5 (SUN50I)\n");
+#elif defined CONFIG_MACH_SUN50I_H6
+       puts("CPU:   Allwinner H6 (SUN50I)\n");
 #else
 #warning Please update cpu_info.c with correct CPU information
        puts("CPU:   SUNXI Family\n");
index 2af26a881af05a3cec061ccdb68e5ee4eb9fa237..0be8ff0d87d7240a92c057e7e27c322b7e4891b0 100644 (file)
@@ -256,7 +256,7 @@ config SPL_SHA256_SUPPORT
 config SPL_FIT_IMAGE_TINY
        bool "Remove functionality from SPL FIT loading to reduce size"
        depends on SPL_FIT
-       default y if MACH_SUN50I || MACH_SUN50I_H5
+       default y if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
        help
          Enable this to reduce the size of the FIT image loading code
          in SPL, if space for the SPL binary is very tight.
diff --git a/include/dt-bindings/clock/sun50i-h6-ccu.h b/include/dt-bindings/clock/sun50i-h6-ccu.h
new file mode 100644 (file)
index 0000000..a1545cd
--- /dev/null
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
+#define _DT_BINDINGS_CLK_SUN50I_H6_H_
+
+#define CLK_PLL_PERIPH0                3
+
+#define CLK_CPUX               21
+
+#define CLK_APB1               26
+
+#define CLK_DE                 29
+#define CLK_BUS_DE             30
+#define CLK_DEINTERLACE                31
+#define CLK_BUS_DEINTERLACE    32
+#define CLK_GPU                        33
+#define CLK_BUS_GPU            34
+#define CLK_CE                 35
+#define CLK_BUS_CE             36
+#define CLK_VE                 37
+#define CLK_BUS_VE             38
+#define CLK_EMCE               39
+#define CLK_BUS_EMCE           40
+#define CLK_VP9                        41
+#define CLK_BUS_VP9            42
+#define CLK_BUS_DMA            43
+#define CLK_BUS_MSGBOX         44
+#define CLK_BUS_SPINLOCK       45
+#define CLK_BUS_HSTIMER                46
+#define CLK_AVS                        47
+#define CLK_BUS_DBG            48
+#define CLK_BUS_PSI            49
+#define CLK_BUS_PWM            50
+#define CLK_BUS_IOMMU          51
+
+#define CLK_MBUS_DMA           53
+#define CLK_MBUS_VE            54
+#define CLK_MBUS_CE            55
+#define CLK_MBUS_TS            56
+#define CLK_MBUS_NAND          57
+#define CLK_MBUS_CSI           58
+#define CLK_MBUS_DEINTERLACE   59
+
+#define CLK_NAND0              61
+#define CLK_NAND1              62
+#define CLK_BUS_NAND           63
+#define CLK_MMC0               64
+#define CLK_MMC1               65
+#define CLK_MMC2               66
+#define CLK_BUS_MMC0           67
+#define CLK_BUS_MMC1           68
+#define CLK_BUS_MMC2           69
+#define CLK_BUS_UART0          70
+#define CLK_BUS_UART1          71
+#define CLK_BUS_UART2          72
+#define CLK_BUS_UART3          73
+#define CLK_BUS_I2C0           74
+#define CLK_BUS_I2C1           75
+#define CLK_BUS_I2C2           76
+#define CLK_BUS_I2C3           77
+#define CLK_BUS_SCR0           78
+#define CLK_BUS_SCR1           79
+#define CLK_SPI0               80
+#define CLK_SPI1               81
+#define CLK_BUS_SPI0           82
+#define CLK_BUS_SPI1           83
+#define CLK_BUS_EMAC           84
+#define CLK_TS                 85
+#define CLK_BUS_TS             86
+#define CLK_IR_TX              87
+#define CLK_BUS_IR_TX          88
+#define CLK_BUS_THS            89
+#define CLK_I2S3               90
+#define CLK_I2S0               91
+#define CLK_I2S1               92
+#define CLK_I2S2               93
+#define CLK_BUS_I2S0           94
+#define CLK_BUS_I2S1           95
+#define CLK_BUS_I2S2           96
+#define CLK_BUS_I2S3           97
+#define CLK_SPDIF              98
+#define CLK_BUS_SPDIF          99
+#define CLK_DMIC               100
+#define CLK_BUS_DMIC           101
+#define CLK_AUDIO_HUB          102
+#define CLK_BUS_AUDIO_HUB      103
+#define CLK_USB_OHCI0          104
+#define CLK_USB_PHY0           105
+#define CLK_USB_PHY1           106
+#define CLK_USB_OHCI3          107
+#define CLK_USB_PHY3           108
+#define CLK_USB_HSIC_12M       109
+#define CLK_USB_HSIC           110
+#define CLK_BUS_OHCI0          111
+#define CLK_BUS_OHCI3          112
+#define CLK_BUS_EHCI0          113
+#define CLK_BUS_XHCI           114
+#define CLK_BUS_EHCI3          115
+#define CLK_BUS_OTG            116
+#define CLK_PCIE_REF_100M      117
+#define CLK_PCIE_REF           118
+#define CLK_PCIE_REF_OUT       119
+#define CLK_PCIE_MAXI          120
+#define CLK_PCIE_AUX           121
+#define CLK_BUS_PCIE           122
+#define CLK_HDMI               123
+#define CLK_HDMI_SLOW          124
+#define CLK_HDMI_CEC           125
+#define CLK_BUS_HDMI           126
+#define CLK_BUS_TCON_TOP       127
+#define CLK_TCON_LCD0          128
+#define CLK_BUS_TCON_LCD0      129
+#define CLK_TCON_TV0           130
+#define CLK_BUS_TCON_TV0       131
+#define CLK_CSI_CCI            132
+#define CLK_CSI_TOP            133
+#define CLK_CSI_MCLK           134
+#define CLK_BUS_CSI            135
+#define CLK_HDCP               136
+#define CLK_BUS_HDCP           137
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */
diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h
new file mode 100644 (file)
index 0000000..7613613
--- /dev/null
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
+
+#define CLK_AR100              0
+
+#define CLK_R_APB1             2
+
+#define CLK_R_APB1_TIMER       4
+#define CLK_R_APB1_TWD         5
+#define CLK_R_APB1_PWM         6
+#define CLK_R_APB2_UART                7
+#define CLK_R_APB2_I2C         8
+#define CLK_R_APB1_IR          9
+#define CLK_R_APB1_W1          10
+
+#define CLK_IR                 11
+#define CLK_W1                 12
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun50i-h6-ccu.h b/include/dt-bindings/reset/sun50i-h6-ccu.h
new file mode 100644 (file)
index 0000000..81106f4
--- /dev/null
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_
+#define _DT_BINDINGS_RESET_SUN50I_H6_H_
+
+#define RST_MBUS               0
+#define RST_BUS_DE             1
+#define RST_BUS_DEINTERLACE    2
+#define RST_BUS_GPU            3
+#define RST_BUS_CE             4
+#define RST_BUS_VE             5
+#define RST_BUS_EMCE           6
+#define RST_BUS_VP9            7
+#define RST_BUS_DMA            8
+#define RST_BUS_MSGBOX         9
+#define RST_BUS_SPINLOCK       10
+#define RST_BUS_HSTIMER                11
+#define RST_BUS_DBG            12
+#define RST_BUS_PSI            13
+#define RST_BUS_PWM            14
+#define RST_BUS_IOMMU          15
+#define RST_BUS_DRAM           16
+#define RST_BUS_NAND           17
+#define RST_BUS_MMC0           18
+#define RST_BUS_MMC1           19
+#define RST_BUS_MMC2           20
+#define RST_BUS_UART0          21
+#define RST_BUS_UART1          22
+#define RST_BUS_UART2          23
+#define RST_BUS_UART3          24
+#define RST_BUS_I2C0           25
+#define RST_BUS_I2C1           26
+#define RST_BUS_I2C2           27
+#define RST_BUS_I2C3           28
+#define RST_BUS_SCR0           29
+#define RST_BUS_SCR1           30
+#define RST_BUS_SPI0           31
+#define RST_BUS_SPI1           32
+#define RST_BUS_EMAC           33
+#define RST_BUS_TS             34
+#define RST_BUS_IR_TX          35
+#define RST_BUS_THS            36
+#define RST_BUS_I2S0           37
+#define RST_BUS_I2S1           38
+#define RST_BUS_I2S2           39
+#define RST_BUS_I2S3           40
+#define RST_BUS_SPDIF          41
+#define RST_BUS_DMIC           42
+#define RST_BUS_AUDIO_HUB      43
+#define RST_USB_PHY0           44
+#define RST_USB_PHY1           45
+#define RST_USB_PHY3           46
+#define RST_USB_HSIC           47
+#define RST_BUS_OHCI0          48
+#define RST_BUS_OHCI3          49
+#define RST_BUS_EHCI0          50
+#define RST_BUS_XHCI           51
+#define RST_BUS_EHCI3          52
+#define RST_BUS_OTG            53
+#define RST_BUS_PCIE           54
+#define RST_PCIE_POWERUP       55
+#define RST_BUS_HDMI           56
+#define RST_BUS_HDMI_SUB       57
+#define RST_BUS_TCON_TOP       58
+#define RST_BUS_TCON_LCD0      59
+#define RST_BUS_TCON_TV0       60
+#define RST_BUS_CSI            61
+#define RST_BUS_HDCP           62
+
+#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */
diff --git a/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/include/dt-bindings/reset/sun50i-h6-r-ccu.h
new file mode 100644 (file)
index 0000000..01c84db
--- /dev/null
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
+
+#define RST_R_APB1_TIMER       0
+#define RST_R_APB1_TWD         1
+#define RST_R_APB1_PWM         2
+#define RST_R_APB2_UART                3
+#define RST_R_APB2_I2C         4
+#define RST_R_APB1_IR          5
+#define RST_R_APB1_W1          6
+
+#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */