arm: mvebu: armada-xp/37x.dtsi: Sync PCIe DT nodes with Linux v4.20
authorStefan Roese <sr@denx.de>
Fri, 25 Jan 2019 10:52:44 +0000 (11:52 +0100)
committerStefan Roese <sr@denx.de>
Tue, 5 Feb 2019 13:22:49 +0000 (14:22 +0100)
This patch sync's the PCIe DT nodes with the recent Linux v4.20 version.
This change makes it easier to reference specific PCIe nodes in the
board dts files to e.g. enable a PCIe port as this is now necessary with
the new DM PCI driver for these platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Marek BehĂșn <marek.behun@nic.cz>
Cc: VlaoMao <vlaomao@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
arch/arm/dts/armada-375.dtsi
arch/arm/dts/armada-xp-mv78230.dtsi
arch/arm/dts/armada-xp-mv78260.dtsi
arch/arm/dts/armada-xp-mv78460.dtsi

index 249c41c7577f425ae94bdea98452018804767a4d..62a548a55f3f7792e6012695b6a28bcf11ac3924 100644 (file)
                        };
                };
 
-               pcie-controller {
+               pciec: pcie@82000000 {
                        compatible = "marvell,armada-370-pcie";
                        status = "disabled";
                        device_type = "pci";
                                0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
                                0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO  */>;
 
-                       pcie@1,0 {
+                       pcie0: pcie@1,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
                                reg = <0x0800 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                                marvell,pcie-port = <0>;
                                status = "disabled";
                        };
 
-                       pcie@2,0 {
+                       pcie1: pcie@2,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
                                reg = <0x1000 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                                marvell,pcie-port = <0>;
index 6e6d0f04bf2b5fe6f5661a75074425b71a3d9fc8..f6bab9fb20a908e305e5c84ca296c9ed22e37dc6 100644 (file)
@@ -86,7 +86,7 @@
                 * configured as x4 or quad x1 lanes. One unit is
                 * x1 only.
                 */
-               pcie-controller {
+               pciec: pcie@82000000 {
                        compatible = "marvell,armada-xp-pcie";
                        status = "disabled";
                        device_type = "pci";
                                0x82000000 0x5 0       MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
                                0x81000000 0x5 0       MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */>;
 
-                       pcie@1,0 {
+                       pcie1: pcie@1,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
                                reg = <0x0800 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 58>;
                                marvell,pcie-port = <0>;
                                status = "disabled";
                        };
 
-                       pcie@2,0 {
+                       pcie2: pcie@2,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
                                reg = <0x1000 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 59>;
                                marvell,pcie-port = <0>;
                                status = "disabled";
                        };
 
-                       pcie@3,0 {
+                       pcie3: pcie@3,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
                                reg = <0x1800 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 60>;
                                marvell,pcie-port = <0>;
                                status = "disabled";
                        };
 
-                       pcie@4,0 {
+                       pcie4: pcie@4,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
                                reg = <0x2000 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 61>;
                                marvell,pcie-port = <0>;
                                status = "disabled";
                        };
 
-                       pcie@5,0 {
+                       pcie5: pcie@5,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
                                reg = <0x2800 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
                                          0x81000000 0 0 0x81000000 0x5 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 62>;
                                marvell,pcie-port = <1>;
index c5fdc99f0dbebb47f88e135a4013fdfb9d732772..d39231f69d9a960f011e27f44974d2afe2f270c3 100644 (file)
@@ -87,7 +87,7 @@
                 * configured as x4 or quad x1 lanes. One unit is
                 * x4 only.
                 */
-               pcie-controller {
+               pciec: pcie@82000000 {
                        compatible = "marvell,armada-xp-pcie";
                        status = "disabled";
                        device_type = "pci";
                                0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
                                0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */>;
 
-                       pcie@1,0 {
+                       pcie1: pcie@1,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
                                reg = <0x0800 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 58>;
                                marvell,pcie-port = <0>;
                                status = "disabled";
                        };
 
-                       pcie@2,0 {
+                       pcie2: pcie@2,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
                                reg = <0x1000 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 59>;
                                marvell,pcie-port = <0>;
                                status = "disabled";
                        };
 
-                       pcie@3,0 {
+                       pcie3: pcie@3,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
                                reg = <0x1800 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 60>;
                                marvell,pcie-port = <0>;
                                status = "disabled";
                        };
 
-                       pcie@4,0 {
+                       pcie4: pcie@4,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
                                reg = <0x2000 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 61>;
                                marvell,pcie-port = <0>;
                                status = "disabled";
                        };
 
-                       pcie@5,0 {
+                       pcie5: pcie@5,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
                                reg = <0x2800 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
                                          0x81000000 0 0 0x81000000 0x5 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 62>;
                                marvell,pcie-port = <1>;
                                status = "disabled";
                        };
 
-                       pcie@6,0 {
+                       pcie6: pcie@6,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
                                reg = <0x3000 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
                                          0x81000000 0 0 0x81000000 0x6 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 63>;
                                marvell,pcie-port = <1>;
                                status = "disabled";
                        };
 
-                       pcie@7,0 {
+                       pcie7: pcie@7,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
                                reg = <0x3800 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
                                          0x81000000 0 0 0x81000000 0x7 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 64>;
                                marvell,pcie-port = <1>;
                                status = "disabled";
                        };
 
-                       pcie@8,0 {
+                       pcie8: pcie@8,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
                                reg = <0x4000 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
                                          0x81000000 0 0 0x81000000 0x8 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 65>;
                                marvell,pcie-port = <1>;
                                status = "disabled";
                        };
 
-                       pcie@9,0 {
+                       pcie9: pcie@9,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
                                reg = <0x4800 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
                                          0x81000000 0 0 0x81000000 0x9 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 99>;
                                marvell,pcie-port = <2>;
index 0e24f1a38540e30ccc257972537c8982074f4c75..c642565d1bc68119dfa5c470fdc7e4d0c63865b0 100644 (file)
                 * configured as x4 or quad x1 lanes. Two units are
                 * x4/x1.
                 */
-               pcie-controller {
+               pciec: pcie@82000000 {
                        compatible = "marvell,armada-xp-pcie";
                        status = "disabled";
                        device_type = "pci";
                                0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
                                0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
 
-                       pcie@1,0 {
+                       pcie1: pcie@1,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
                                reg = <0x0800 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 58>;
                                marvell,pcie-port = <0>;
                                status = "disabled";
                        };
 
-                       pcie@2,0 {
+                       pcie2: pcie@2,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
                                reg = <0x1000 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 59>;
                                marvell,pcie-port = <0>;
                                status = "disabled";
                        };
 
-                       pcie@3,0 {
+                       pcie3: pcie@3,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
                                reg = <0x1800 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 60>;
                                marvell,pcie-port = <0>;
                                status = "disabled";
                        };
 
-                       pcie@4,0 {
+                       pcie4: pcie@4,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
                                reg = <0x2000 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 61>;
                                marvell,pcie-port = <0>;
                                status = "disabled";
                        };
 
-                       pcie@5,0 {
+                       pcie5: pcie@5,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
                                reg = <0x2800 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
                                          0x81000000 0 0 0x81000000 0x5 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 62>;
                                marvell,pcie-port = <1>;
                                status = "disabled";
                        };
 
-                       pcie@6,0 {
+                       pcie6: pcie@6,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
                                reg = <0x3000 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
                                          0x81000000 0 0 0x81000000 0x6 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 63>;
                                marvell,pcie-port = <1>;
                                status = "disabled";
                        };
 
-                       pcie@7,0 {
+                       pcie7: pcie@7,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
                                reg = <0x3800 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
                                          0x81000000 0 0 0x81000000 0x7 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 64>;
                                marvell,pcie-port = <1>;
                                status = "disabled";
                        };
 
-                       pcie@8,0 {
+                       pcie8: pcie@8,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
                                reg = <0x4000 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
                                          0x81000000 0 0 0x81000000 0x8 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 65>;
                                marvell,pcie-port = <1>;
                                status = "disabled";
                        };
 
-                       pcie@9,0 {
+                       pcie9: pcie@9,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
                                reg = <0x4800 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
                                          0x81000000 0 0 0x81000000 0x9 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 99>;
                                marvell,pcie-port = <2>;
                                status = "disabled";
                        };
 
-                       pcie@10,0 {
+                       pcie10: pcie@a,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
                                reg = <0x5000 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
                                          0x81000000 0 0 0x81000000 0xa 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 103>;
                                marvell,pcie-port = <3>;