arm: Remove vl_ma2sc board
authorSimon Glass <sjg@chromium.org>
Mon, 31 Aug 2015 01:19:32 +0000 (19:19 -0600)
committerTom Rini <trini@konsulko.com>
Fri, 11 Sep 2015 21:12:57 +0000 (17:12 -0400)
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
arch/arm/mach-at91/Kconfig
board/BuS/vl_ma2sc/Kconfig [deleted file]
board/BuS/vl_ma2sc/MAINTAINERS [deleted file]
board/BuS/vl_ma2sc/Makefile [deleted file]
board/BuS/vl_ma2sc/vl_ma2sc.c [deleted file]
configs/vl_ma2sc_defconfig [deleted file]
configs/vl_ma2sc_ram_defconfig [deleted file]
include/configs/vl_ma2sc.h [deleted file]

index 26ba5ace03a5462472eda8ba6b1c579409943a50..fdaf3287220662e1da8170adeeed48d83def8cf7 100644 (file)
@@ -91,10 +91,6 @@ config TARGET_SAMA5D4EK
        select CPU_V7
        select SUPPORT_SPL
 
-config TARGET_VL_MA2SC
-       bool "Support vl_ma2sc"
-       select CPU_ARM926EJS
-
 config TARGET_MEESC
        bool "Support meesc"
        select CPU_ARM926EJS
@@ -132,7 +128,6 @@ source "board/atmel/sama5d3xek/Kconfig"
 source "board/atmel/sama5d4_xplained/Kconfig"
 source "board/atmel/sama5d4ek/Kconfig"
 source "board/bluewater/snapper9260/Kconfig"
-source "board/BuS/vl_ma2sc/Kconfig"
 source "board/calao/usb_a9263/Kconfig"
 source "board/egnite/ethernut5/Kconfig"
 source "board/esd/meesc/Kconfig"
diff --git a/board/BuS/vl_ma2sc/Kconfig b/board/BuS/vl_ma2sc/Kconfig
deleted file mode 100644 (file)
index 848177f..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_VL_MA2SC
-
-config SYS_BOARD
-       default "vl_ma2sc"
-
-config SYS_VENDOR
-       default "BuS"
-
-config SYS_CONFIG_NAME
-       default "vl_ma2sc"
-
-endif
diff --git a/board/BuS/vl_ma2sc/MAINTAINERS b/board/BuS/vl_ma2sc/MAINTAINERS
deleted file mode 100644 (file)
index b70104d..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-VL_MA2SC BOARD
-M:     Jens Scharsig <esw@bus-elektronik.de>
-S:     Maintained
-F:     board/BuS/vl_ma2sc/
-F:     include/configs/vl_ma2sc.h
-F:     configs/vl_ma2sc_defconfig
-F:     configs/vl_ma2sc_ram_defconfig
diff --git a/board/BuS/vl_ma2sc/Makefile b/board/BuS/vl_ma2sc/Makefile
deleted file mode 100644 (file)
index d4b24ac..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2009-2012
-# Jens Scharsig  <esw@bus-elekronik.de>
-# BuS Elektronik GmbH & Co. KG
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y += vl_ma2sc.o
diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c
deleted file mode 100644 (file)
index e4e1a85..0000000
+++ /dev/null
@@ -1,519 +0,0 @@
-/*
- * (C) Copyright 2009-2012
- * Jens Scharsig  <esw@bus-elekronik.de>
- * BuS Elektronik GmbH & Co. KG
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <linux/sizes.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/at91_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/at91sam9263.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91_common.h>
-#include <lcd.h>
-#include <i2c.h>
-#include <atmel_lcdc.h>
-#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
-#include <net.h>
-#endif
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_CMD_NAND
-static void vl_ma2sc_nand_hw_init(void)
-{
-       unsigned long csa;
-       at91_smc_t      *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
-       at91_matrix_t   *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
-       at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
-
-       at91_set_pio_output(AT91_PIO_PORTA, 13, 1);     /* CAN_TX -> H */
-       at91_set_pio_output(AT91_PIO_PORTA, 12, 1);     /* CAN_STB -> H */
-       at91_set_pio_output(AT91_PIO_PORTA, 11, 1);     /* CAN_EN -> H */
-
-       /* Enable CS3 */
-       csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
-       writel(csa, &matrix->csa[0]);
-
-       /* Configure SMC CS3 for NAND/SmartMedia */
-       writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
-               AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
-               &smc->cs[3].setup);
-
-       writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
-               AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
-               &smc->cs[3].pulse);
-
-       writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
-               &smc->cs[3].cycle);
-       writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
-               AT91_SMC_MODE_DBW_8 |
-               AT91_SMC_MODE_TDF_CYCLE(2),
-               &smc->cs[3].mode);
-       writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE),
-               &pmc->pcer);
-
-       /* Configure RDY/BSY */
-#ifdef CONFIG_SYS_NAND_READY_PIN
-       gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
-#endif
-       /* Enable NandFlash */
-       gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-}
-#endif
-
-#ifdef CONFIG_MACB
-static void vl_ma2sc_macb_hw_init(void)
-{
-       at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
-
-       /* Enable clock */
-       writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
-
-       at91_phy_reset();
-
-       at91_macb_hw_init();
-}
-#endif
-
-#ifdef CONFIG_LCD
-vidinfo_t panel_info = {
-       .vl_col =               320,
-       .vl_row =               240,
-       .vl_clk =               6500000,
-       .vl_sync =              ATMEL_LCDC_INVDVAL_INVERTED |
-                               ATMEL_LCDC_INVLINE_INVERTED |
-                               ATMEL_LCDC_INVVD_INVERTED   |
-                               ATMEL_LCDC_INVFRAME_INVERTED,
-       .vl_bpix =              (ATMEL_LCDC_PIXELSIZE_8 >> 5),
-       .vl_tft =               1,
-       .vl_hsync_len =         5,      /* Horiz Sync Pulse Width */
-       .vl_left_margin =       68,     /* horiz back porch */
-       .vl_right_margin =      20,     /* horiz front porch */
-       .vl_vsync_len =         2,      /* vert Sync Pulse Width */
-       .vl_upper_margin =      18,     /* vert back porch */
-       .vl_lower_margin =      4,      /* vert front porch */
-       .mmio =                 ATMEL_BASE_LCDC,
-};
-
-void lcd_enable(void)
-{
-}
-
-void lcd_disable(void)
-{
-}
-
-static void vl_ma2sc_lcd_hw_init(void)
-{
-       at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
-
-       at91_set_a_periph(AT91_PIO_PORTC, 0, 0);        /* LCDVSYNC */
-       at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* LCDHSYNC */
-       at91_set_a_periph(AT91_PIO_PORTC, 2, 0);        /* LCDDOTCK */
-       at91_set_a_periph(AT91_PIO_PORTC, 3, 0);        /* LCDDEN */
-       at91_set_b_periph(AT91_PIO_PORTB, 9, 0);        /* LCDCC */
-
-       at91_set_a_periph(AT91_PIO_PORTC, 4, 0);        /* LCDD0 */
-       at91_set_a_periph(AT91_PIO_PORTC, 5, 0);        /* LCDD1 */
-       at91_set_a_periph(AT91_PIO_PORTC, 6, 0);        /* LCDD2 */
-       at91_set_a_periph(AT91_PIO_PORTC, 7, 0);        /* LCDD3 */
-       at91_set_a_periph(AT91_PIO_PORTC, 8, 0);        /* LCDD4 */
-       at91_set_a_periph(AT91_PIO_PORTC, 9, 0);        /* LCDD5 */
-       at91_set_a_periph(AT91_PIO_PORTC, 10, 0);       /* LCDD6 */
-       at91_set_a_periph(AT91_PIO_PORTC, 11, 0);       /* LCDD7 */
-
-       at91_set_a_periph(AT91_PIO_PORTC, 13, 0);       /* LCDD9 */
-       at91_set_a_periph(AT91_PIO_PORTC, 14, 0);       /* LCDD10 */
-       at91_set_a_periph(AT91_PIO_PORTC, 15, 0);       /* LCDD11 */
-       at91_set_a_periph(AT91_PIO_PORTC, 16, 0);       /* LCDD12 */
-       at91_set_b_periph(AT91_PIO_PORTC, 12, 0);       /* LCDD13 */
-       at91_set_a_periph(AT91_PIO_PORTC, 18, 0);       /* LCDD14 */
-       at91_set_a_periph(AT91_PIO_PORTC, 19, 0);       /* LCDD15 */
-
-       at91_set_a_periph(AT91_PIO_PORTC, 20, 0);       /* LCDD26 */
-       at91_set_a_periph(AT91_PIO_PORTC, 21, 0);       /* LCDD17 */
-       at91_set_a_periph(AT91_PIO_PORTC, 22, 0);       /* LCDD18 */
-       at91_set_a_periph(AT91_PIO_PORTC, 23, 0);       /* LCDD19 */
-       at91_set_a_periph(AT91_PIO_PORTC, 24, 0);       /* LCDD20 */
-       at91_set_b_periph(AT91_PIO_PORTC, 17, 0);       /* LCDD21 */
-       at91_set_a_periph(AT91_PIO_PORTC, 26, 0);       /* LCDD22 */
-       at91_set_a_periph(AT91_PIO_PORTC, 27, 0);       /* LCDD23 */
-
-       at91_set_pio_output(AT91_PIO_PORTE, 0, 0);      /* LCD QXH */
-
-       at91_set_pio_output(AT91_PIO_PORTE, 2, 0);      /* LCD SHUT */
-       at91_set_pio_output(AT91_PIO_PORTE, 3, 1);      /* LCD TopBottom */
-       at91_set_pio_output(AT91_PIO_PORTE, 4, 0);      /* LCD REV */
-       at91_set_pio_output(AT91_PIO_PORTE, 5, 1);      /* LCD RightLeft */
-       at91_set_pio_output(AT91_PIO_PORTE, 6, 0);      /* LCD Color Mode CM */
-       at91_set_pio_output(AT91_PIO_PORTE, 7, 0);      /* LCD BGR */
-
-       at91_set_pio_output(AT91_PIO_PORTB, 9, 0);      /* LCD CC */
-
-       writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
-       gd->fb_base = ATMEL_BASE_SRAM0;
-}
-#endif /* Config LCD */
-
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
-{
-       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-       /* Enable clocks for all PIOs */
-       writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
-               (1 << ATMEL_ID_PIOCDE),
-               &pmc->pcer);
-
-       at91_seriald_hw_init();
-
-       return 0;
-}
-#endif
-
-int board_init(void)
-{
-       at91_smc_t      *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
-       at91_pio_t      *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-       u32             pin;
-
-       pin = 0x1F000001;
-       writel(pin, &pio->pioa.idr);
-       writel(pin, &pio->pioa.pudr);
-       writel(pin, &pio->pioa.per);
-       writel(pin, &pio->pioa.oer);
-       writel(pin, &pio->pioa.sodr);
-       writel((1 << 25), &pio->pioa.codr);
-
-       pin = 0x1F000100;
-       writel(pin, &pio->piob.idr);
-       writel(pin, &pio->piob.pudr);
-       writel(pin, &pio->piob.per);
-       writel(pin, &pio->piob.oer);
-       writel(pin, &pio->piob.codr);
-       writel((1 << 24), &pio->piob.sodr);
-
-       pin = 0x40000000;                       /* Pullup DRxD enbable */
-       writel(pin, &pio->pioc.puer);
-
-       pin = 0x0000000F;                       /* HWversion als Input */
-       writel(pin, &pio->piod.idr);
-       writel(pin, &pio->piod.puer);
-       writel(pin, &pio->piod.per);
-       writel(pin, &pio->piod.odr);
-       writel(pin, &pio->piod.owdr);
-
-       gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC;
-       /* adress of boot parameters */
-       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-       writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup);
-       writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle);
-       writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse);
-       writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup);
-
-#ifdef CONFIG_CMD_NAND
-       vl_ma2sc_nand_hw_init();
-#endif
-#ifdef CONFIG_MACB
-       vl_ma2sc_macb_hw_init();
-#endif
-#ifdef CONFIG_USB_OHCI_NEW
-       at91_uhp_hw_init();
-#endif
-#ifdef CONFIG_LCD
-       vl_ma2sc_lcd_hw_init();
-#endif
-       return 0;
-}
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
-       uchar   buffer[8];
-       at91_pio_t      *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-       u32             pin;
-
-       buffer[0] = 0x04;
-       buffer[1] = 0x00;
-       if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0)
-               puts("error reseting rtc clock\n\0");
-
-       /* read hardware version */
-
-       pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44;
-       printf("Board: revision %c\n", pin);
-       buffer[0] = pin;
-       buffer[1] = 0;
-       setenv("revision", (char *) buffer);
-
-       pin = 0x40000000;                       /* Pullup DRxD enbable */
-       writel(pin, &pio->pioc.puer);
-       return 0;
-}
-#endif
-
-int dram_init(void)
-{
-       gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
-                       CONFIG_SYS_SDRAM_SIZE);
-       return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-void reset_phy(void)
-{
-#ifdef CONFIG_MACB
-       /*
-        * Initialize ethernet HW addr prior to starting Linux,
-        * needed for nfsroot
-        */
-       eth_init();
-#endif
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-       int rc = 0;
-#ifdef CONFIG_MACB
-       rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01);
-#endif
-       return rc;
-}
-
-#ifdef CONFIG_SYS_I2C_SOFT
-void i2c_init_board(void)
-{
-       u32 pin;
-
-       at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-       at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-       u8 sda = (1<<4);
-       u8 scl = (1<<5);
-
-       writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
-       pin = sda | scl;
-       writel(pin, &pio->piob.idr);    /* Disable Interupt */
-       writel(pin, &pio->piob.pudr);
-       writel(pin, &pio->piob.per);
-       writel(pin, &pio->piob.oer);
-       writel(pin, &pio->piob.sodr);
-}
-#endif
-
-void watchdog_reset(void)
-{
-       at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-       u32     pin = 0x1;      /* PA0 */
-
-       if ((readl(&pio->pioa.odsr) & pin) > 0)
-               writel(pin, &pio->pioa.codr);
-       else
-               writel(pin, &pio->pioa.sodr);
-}
-
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_DCACHE_OFF
-       dcache_enable();
-#endif
-}
-
-/*---------------------------------------------------------------------------*/
-
-int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-       int rcode = 1;
-       int row;
-       int col;
-       u32 pinz;
-       u32 pins;
-       at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-
-       at91_set_pio_output(AT91_PIO_PORTB, 8, 0);      /* LCD DIM */
-
-       pins = 0x1F000000;
-       writel(pins, &pio->pioa.idr);
-       writel(pins, &pio->pioa.pudr);
-       writel(pins, &pio->pioa.per);
-       writel(pins, &pio->pioa.oer);
-       writel(pins, &pio->pioa.sodr);
-
-       pinz = 0x1F000000;
-       writel(pinz, &pio->piob.idr);
-       writel(pinz, &pio->piob.pudr);
-       writel(pinz, &pio->piob.per);
-       writel(pinz, &pio->piob.oer);
-       writel(pinz, &pio->piob.sodr);
-
-       for (row = 0; row < 5; row++) {
-               for (col = 0; col < 5; col++) {
-                       writel((0x01000000 << col), &pio->piob.sodr);
-                       writel((0x01000000 << row), &pio->pioa.codr);
-                       printf("LED Test %d x %d\n", row, col);
-                       udelay(1000000);
-                       writel(pinz, &pio->piob.codr);
-                       writel(pins, &pio->pioa.sodr);
-               }
-       }
-       return rcode;
-}
-
-void poweroff(void)
-{
-       watchdog_reset();
-       at91_set_pio_output(AT91_PIO_PORTA, 13, 1);     /* CAN_TX -> H */
-       udelay(100);
-       at91_set_pio_output(AT91_PIO_PORTA, 12, 0);     /* CAN_STB -> L */
-       udelay(100);
-       at91_set_pio_output(AT91_PIO_PORTA, 11, 0);     /* CAN_EN -> L */
-       udelay(100);
-       while (1)
-               watchdog_reset();
-}
-
-int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc,  char * const argv[])
-{
-       int rcode = 1;
-       poweroff();
-       return rcode;
-}
-
-int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-       int i;
-       u32 freq;
-       u32 durate;
-       int rcode = 1;
-
-       freq = 1000;
-       durate = 2;
-       switch (argc) {
-       case 3:
-               durate = simple_strtoul(argv[2], NULL, 10);
-       case 2:
-               freq = simple_strtoul(argv[1], NULL, 10);
-       case 1:
-               break;
-       default:
-               cmd_usage(cmdtp);
-               rcode = 1;
-               break;
-       }
-       durate = durate * freq;
-       freq = 500000 / freq;
-       for (i = 0; i < durate; i++) {
-               at91_set_pio_output(AT91_PIO_PORTB, 29, 1);     /* Sound On*/
-               udelay(freq);
-               at91_set_pio_output(AT91_PIO_PORTB, 29, 0);     /* Sound Off*/
-               udelay(freq);
-       }
-       at91_set_pio_output(AT91_PIO_PORTB, 29, 0);     /* Sound Off*/
-       return rcode;
-}
-
-int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-       int rcode = 1;
-       int row;
-       u32 col;
-       u32 pinz;
-       u32 pins;
-       at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-       at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
-       writel((1 << ATMEL_ID_PIOA), &pmc->pcer);
-
-       pins = 0x001F0000;
-       writel(pins, &pio->pioa.idr);
-       writel(pins, &pio->pioa.pudr);
-       writel(pins, &pio->pioa.per);
-       writel(pins, &pio->pioa.odr);
-
-       pinz = 0x000F0000;
-       writel(pinz, &pio->piob.idr);
-       writel(pinz, &pio->piob.pudr);
-       writel(pinz, &pio->piob.per);
-       writel(pinz, &pio->piob.oer);
-       writel(pinz, &pio->piob.codr);
-
-       while (1) {
-               col = 0;
-               for (row = 0; row < 4; row++) {
-                       writel((0x00010000 << row), &pio->piob.sodr);
-                       udelay(10000);
-                       col <<= 4;
-                       col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ;
-                       writel(pinz, &pio->piob.codr);
-               }
-               printf("Matix: ");
-               for (row = 0; row < 16; row++) {
-                       printf("%1.1d", col & 1);
-                       col >>= 1;
-               }
-               printf(" SP %d\r ",
-                       1 ^ (1 & (readl(&pio->piob.pdsr) >> 20)));
-               if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) {
-                       /* SHUTDOWN */
-                       row = 0;
-                       while (row < 1000) {
-                               if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0)
-                                       row++;
-                               udelay(100);
-                       }
-                       udelay(100000);
-                       row = 0;
-                       while (row < 1000) {
-                               if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) {
-                                       row++;
-                                       udelay(1000);
-                               }
-                       }
-                       poweroff();
-                       while (1)
-                               ;
-               }
-       }
-       return rcode;
-}
-
-/*****************************************************************************/
-
-U_BOOT_CMD(
-       ledtest,        1,      0,      do_ledtest,
-       "test ledmatrix",
-       "\n"
-       );
-
-U_BOOT_CMD(
-       keytest,        1,      0,      do_keytest,
-       "test keymatix and special keys, poweroff on pressing ON key",
-       "\n"
-       );
-
-U_BOOT_CMD(
-       poweroff,       1,      0,      do_poweroff,
-       "power off",
-       "\n"
-       );
-
-U_BOOT_CMD(
-       beep,   3,      0,      do_beep,
-       "[freq [duration]]",
-       "freq frequence of beep\nduration duration of beep\n"
-       );
-
-/*****************************************************************************/
diff --git a/configs/vl_ma2sc_defconfig b/configs/vl_ma2sc_defconfig
deleted file mode 100644 (file)
index c908c6e..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_VL_MA2SC=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/vl_ma2sc_ram_defconfig b/configs/vl_ma2sc_ram_defconfig
deleted file mode 100644 (file)
index 43a576f..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_VL_MA2SC=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMLOAD"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h
deleted file mode 100644 (file)
index 3facd7f..0000000
+++ /dev/null
@@ -1,429 +0,0 @@
-/*
- * (C) Copyright 2009-2012
- * Jens Scharsig  <esw@bus-elekronik.de>
- * BuS Elektronik GmbH & Co. KG
- *
- * Configuation settings for the VL_MA2SC board.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*--------------------------------------------------------------------------*/
-
-#define CONFIG_AT91SAM9263             /* It's an Atmel AT91SAM9263 SoC*/
-#define CONFIG_VL_MA2SC                        /* on an VL_MA2SC Board */
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_MISC_INIT_R
-
-#include <asm/hardware.h>
-
-#define MACH_TYPE_VL_MA2SC             2412
-#define CONFIG_MACH_TYPE               MACH_TYPE_VL_MA2SC
-
-#define CONFIG_SYS_DCACHE_OFF
-
-#ifdef CONFIG_RAMLOAD
-#define CONFIG_SYS_TEXT_BASE           0x21000000
-#else
-#define CONFIG_SYS_TEXT_BASE           0x00000000
-#endif
-#define CONFIG_SYS_LOAD_ADDR           0x21000000  /* default load address */
-
-#define CONFIG_IDENT_STRING            " on MiS Activ 2"
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AT91_GPIO
-
-#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD)
-#define CONFIG_SYS_USE_NORFLASH
-#define CONFIG_SYS_USE_BOOT_NORFLASH
-#endif
-
-#define CONFIG_CMDLINE_TAG                     /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_WATCHDOG
-
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE              ATMEL_BASE_DBGU
-#define CONFIG_USART_ID                        ATMEL_ID_SYS
-
-/* LCD */
-#define CONFIG_LCD
-#define CONFIG_ATMEL_LCD
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SYS_BLACK_ON_WHITE
-#define LCD_BPP                                LCD_COLOR8
-#define CONFIG_ATMEL_LCD_BGR555
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_BOOTDELAY               3
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_BMP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_MD5SUM
-#define CONFIG_CMD_SHA1SUM
-/*
-#define CONFIG_CMD_SPI
-*/
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_USB
-
-#define        CONFIG_SYS_LONGHELP
-#define CONFIG_MD5
-#define        CONFIG_SHA1
-
-/*----------------------------------------------------------------------------
- * Hardware confuguration
- *---------------------------------------------------------------------------*/
-
-/* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE          0x00a00000      /* UHP_BASE */
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME          "at91sam9263"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     2
-#define CONFIG_USB_STORAGE
-#define CONFIG_AT91C_PQFP_UHPBUG
-
-/* I2C-Bus */
-
-#define CONFIG_SYS_I2C_SPEED                   50000
-#define CONFIG_SYS_I2C_SLAVE                   0               /* not used */
-
-#ifndef CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT                    /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED      CONFIG_SYS_I2C_SPEED
-#define CONFIG_SYS_I2C_SOFT_SLAVE      CONFIG_SYS_I2C_SLAVE
-
-/* Software  I2C driver configuration */
-#define I2C_DELAY      udelay(2500000/CONFIG_SYS_I2C_SPEED)
-
-#define AT91_PIN_SDA   (1<<4)          /* AT91C_PIO_PB4 */
-#define AT91_PIN_SCL   (1<<5)          /* AT91C_PIO_PB5 */
-
-#define I2C_INIT       i2c_init_board();
-#define I2C_ACTIVE     writel(AT91_PIN_SDA, &pio->piob.mddr);
-#define I2C_TRISTATE   writel(AT91_PIN_SDA, &pio->piob.mder);
-#define I2C_READ       ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0)
-#define I2C_SDA(bit)                                           \
-       do {                                                    \
-               if (bit)                                        \
-                       writel(AT91_PIN_SDA, &pio->piob.sodr);  \
-               else                                            \
-                       writel(AT91_PIN_SDA, &pio->piob.codr);  \
-       } while (0);
-#define I2C_SCL(bit)                                           \
-       do {                                                    \
-               if (bit)                                        \
-                       writel(AT91_PIN_SCL, &pio->piob.sodr);  \
-               else                                            \
-                       writel(AT91_PIN_SCL, &pio->piob.codr);  \
-       } while (0);
-#endif
-
-/* I2C-RTC */
-
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_DS1338
-#define CONFIG_SYS_I2C_RTC_ADDR        0x68
-#endif
-
-/* EEPROM */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR     0x50
-
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1       0xFFFF0000
-#define CONFIG_SYS_PIOD_PPUDR_VAL      0xFFFF0000
-
-/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL                                  \
-       (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |       \
-        AT91_MATRIX_CSA_EBI_CS1A)
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL                        \
-               (AT91_RSTC_KEY |                \
-               AT91_RSTC_MR_URSTEN |           \
-               AT91_RSTC_MR_ERSTL(15))
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL                               \
-               (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
-                AT91_WDT_MR_WDV(0xFFF) |                       \
-                AT91_WDT_MR_WDDIS |                            \
-                AT91_WDT_MR_WDD(0xFFF))
-
-/* clocks */
-
-#define CONFIG_SYS_AT91_SLOW_CLOCK     32768           /* slow clock */
-
-#define MHZ180
-#if defined(MHZ199)
-/* 199,8994 MHZ */
-#define MASTER_PLL_MUL         911
-#define MASTER_PLL_DIV         56
-#define MASTER_PLL_OUT         2
-#elif defined(MHZ180)
-/* 180 MHZ */
-#define MASTER_PLL_MUL         1875
-#define MASTER_PLL_DIV         128
-#define MASTER_PLL_OUT         2
-#elif defined(MHZTEST)
-/* Test MHZ */
-#define CONFIG_DISPLAY_CPUINFO
-#define MASTER_PLL_MUL         8
-#define MASTER_PLL_DIV         1
-#define MASTER_PLL_OUT         2
-#else
-/* 176.9472 MHZ */
-#define MASTER_PLL_MUL         72
-#define MASTER_PLL_DIV         5
-#define MASTER_PLL_OUT         2
-#endif
-
-#define CONFIG_SYS_MOR_VAL                                     \
-       (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
-
-#define CONFIG_SYS_PLLAR_VAL                                   \
-       (AT91_PMC_PLLAR_29 |                                    \
-       AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |                    \
-       AT91_PMC_PLLXR_PLLCOUNT(63) |                           \
-       AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) |                \
-       AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define        CONFIG_SYS_MCKR1_VAL            \
-       (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |        \
-        AT91_PMC_MCKR_MDIV_2)
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define        CONFIG_SYS_MCKR2_VAL            \
-       (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 |        \
-       AT91_PMC_MCKR_MDIV_2)
-
-/* SDRAM */
-#define CONFIG_NR_DRAM_BANKS           1
-#define CONFIG_SYS_SDRAM_BASE          0x20000000
-#define CONFIG_SYS_SDRAM_SIZE          0x04000000  /* 64 megs */
-#define CONFIG_SYS_INIT_SP_ADDR                0x00504000  /* use internal SRAM0 */
-
-#define CONFIG_SYS_SDRC_MR_VAL1                0
-#define CONFIG_SYS_SDRC_TR_VAL1                700
-#define CONFIG_SYS_SDRC_CR_VAL                                         \
-               (AT91_SDRAMC_NC_9 |                                     \
-                AT91_SDRAMC_NR_13 |                                    \
-                AT91_SDRAMC_NB_4 |                                     \
-                AT91_SDRAMC_CAS_3 |                                    \
-                AT91_SDRAMC_DBW_32 |                                   \
-                (2 <<  8) |            /* Write Recovery Delay */      \
-                (7 << 12) |            /* Row Cycle Delay */           \
-                (2 << 16) |            /* Row Precharge Delay */       \
-                (2 << 20) |            /* Row to Column Delay */       \
-                (5 << 24) |            /* Active to Precharge Delay */ \
-                (8 << 28))             /* Exit Self Refresh to Active Delay */
-
-#define CONFIG_SYS_SDRC_MDR_VAL                AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2                AT91_SDRAMC_MODE_PRECHARGE
-#define CONFIG_SYS_SDRAM_VAL1          0               /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3                AT91_SDRAMC_MODE_REFRESH
-#define CONFIG_SYS_SDRAM_VAL2          0               /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL3          0               /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL4          0               /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL5          0               /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL6          0               /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL7          0               /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL8          0               /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL9          0               /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4                AT91_SDRAMC_MODE_LMR
-#define CONFIG_SYS_SDRAM_VAL10         0               /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5                AT91_SDRAMC_MODE_NORMAL
-#define CONFIG_SYS_SDRAM_VAL11         0               /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2                1200            /* SDRAM_TR */
-#define CONFIG_SYS_SDRAM_VAL12         0               /* SDRAM_BASE */
-
-/* NOR flash */
-
-#define CONFIG_FLASH_SHOW_PROGRESS     45
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define PHYS_FLASH_1                   0x10000000
-#define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_SECT      256
-#define CONFIG_SYS_MAX_FLASH_BANKS     1
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR                        (CONFIG_SYS_FLASH_BASE + 0x00060000)
-
-/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL                             \
-       (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
-        AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
-#define CONFIG_SYS_SMC0_PULSE0_VAL                             \
-       (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
-        AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL     \
-       (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
-#define CONFIG_SYS_SMC0_MODE0_VAL                              \
-       (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |          \
-        AT91_SMC_MODE_DBW_16 |                                 \
-        AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
-
-/* NAND flash */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_ATMEL
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_SYS_NAND_BASE           0x40000000
-#define CONFIG_SYS_NAND_DBW_8          1
-#define CONFIG_SYS_NAND_MASK_ALE       (1 << 21)       /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE       (1 << 22)       /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_ENABLE_PIN     GPIO_PIN_PD(15)
-#define CONFIG_SYS_NAND_READY_PIN      GPIO_PIN_PB(0)
-#endif
-
-/* Ethernet */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT         5
-#define CONFIG_AT91_WANTS_COMMON_PHY
-
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-#define CONFIG_SYS_LOAD_ADDR           0x21000000  /* default load address */
-
-#define CONFIG_SYS_MEMTEST_START       CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END         0x21e00000
-
-/* Address and size of Primary Environment Sector */
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE                        0x20000
-#else
-#define CONFIG_ENV_SIZE                        0x2000
-#endif
-
-#define CONFIG_BAUDRATE                        115200
-#define CONFIG_SYS_BAUDRATE_TABLE      {312500, 230400, 115200, 19200, \
-                                               38400, 57600, 9600 }
-
-#define CONFIG_SYS_CBSIZE      512             /* Console I/O Buffer Size */
-#define CONFIG_SYS_MAXARGS     32              /* max number of command args */
-#define CONFIG_SYS_PBSIZE      \
-       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN          \
-       ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-
-#ifndef CONFIG_RAMLOAD
-#define CONFIG_BOOTCOMMAND             "run nfsboot"
-#endif
-#define CONFIG_BOOT_RETRY_TIME         -1
-#define CONFIG_BOOT_RETRY_MIN          15
-
-#define CONFIG_NFSBOOTCOMMAND                                          \
-               "dhcp $(copy_addr) $(kernelname);"                      \
-               "run bootargsdefaults;"                                 \
-               "set bootargs $(bootargs) boot=nfs "                    \
-               ";echo $(bootargs)"                                     \
-       ";bootm"
-
-#define CONFIG_EXTRA_ENV_SETTINGS                                      \
-       "ubootaddr=10000000\0"                                          \
-       "splashimage=10080000\0"                                        \
-       "kerneladdr=100A0000\0"                                         \
-       "kernelsize=00800000\0"                                         \
-       "minifsaddr=108A0000\0"                                         \
-       "minifssize=00060000\0"                                         \
-       "rootfsaddr=10900000\0"                                         \
-       "copy_addr=20200000\0"                                          \
-       "rootfssize=01700000\0"                                         \
-       "kernelname=uImage_vl_ma2sc\0"                                  \
-       "bootargsdefaults=set bootargs "                                \
-               "console=ttyS0,115200 "                                 \
-               "video=atmel_lcdfb "                                    \
-               "mem=62M "                                              \
-               "panic=10 "                                             \
-               "boardrevison=\\\"${revision}\\\" "                     \
-               "uboot=\\\"${ver}\\\" "                                 \
-               "\0"                                                    \
-       "update_all=run update_kernel;run update_root;"                 \
-               "run update_splash; run update_uboot\0"                 \
-       "update_kernel=protect off $(kerneladdr) +$(kernelsize);"       \
-               "dhcp $(copy_addr) $(kernelname);"                      \
-               "erase $(kerneladdr) +$(kernelsize);"                   \
-               "cp.b $(fileaddr) $(kerneladdr) $(filesize);"           \
-               "protect on $(kerneladdr) +$(kernelsize)"               \
-               "\0"                                                    \
-       "update_root=protect off $(rootfsaddr) +$(rootfssize);"         \
-               "dhcp $(copy_addr) vl_ma2sc.root;"                      \
-               "erase $(rootfsaddr) +$(rootfssize);"                   \
-               "cp.b $(fileaddr) $(rootfsaddr) $(filesize);"           \
-               "\0"                                                    \
-       "update_splash=protect off $(splashimage) +20000;"              \
-               "dhcp $(copy_addr) splash_vl_ma2sc.bmp;"                \
-               "erase $(splashimage) +20000;"                          \
-               "cp.b $(fileaddr) 10080000 $(filesize);"                \
-               "protect on $(splashimage) +20000\0"                    \
-       "update_uboot=protect off 10000000 1005FFFF;"                   \
-               "dhcp $(copy_addr) u-boot_vl_ma2sc;"                    \
-               "erase 10000000 1005FFFF;"                              \
-               "cp.b $(fileaddr) $(ubootaddr) $(filesize);"            \
-               "protect on 10000000 1005FFFF;reset\0"                  \
-       "emergency=run bootargsdefaults;"                               \
-               "set bootargs $(bootargs) root=initramfs boot=emergency " \
-               ";bootm $(kerneladdr)\0"                                \
-       "netemergency=run bootargsdefaults;"                            \
-               "dhcp $(copy_addr) $(kernelname);"                      \
-               "set bootargs $(bootargs) root=initramfs boot=emergency " \
-               ";bootm $(copy_addr)\0"                                 \
-       "norboot=run bootargsdefaults;"                                 \
-               "set bootargs $(bootargs) root=initramfs boot=local quiet " \
-               ";bootm $(kerneladdr)\0"                                \
-       "nandboot=run bootargsdefaults;"                                \
-               "set bootargs $(bootargs) root=initramfs boot=nand "    \
-               ";bootm $(kerneladdr)\0"                                \
-       "setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0"  \
-       "clearenv=protect off 10060000 1007FFFF;"                       \
-               "erase 10060000 1007FFFF;reset\0"                       \
-       " "
-
-#endif