ARM: zynq: slcr: Fix incorrect commentary

Fix c&p error in zynq_slcr_devcfg_enable() commentary
and extending it with description according
to Zynq TRM also in zynq_slcr_devcfg_disable().

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index c326a4c5de3b5a7382a2eccc12c1e737d0470bea..1ff1eac06f9a258462600074e1ef7faa02af8e44 100644 (file)
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -83,7 +83,7 @@ void zynq_slcr_devcfg_disable(void)
 {
        zynq_slcr_unlock();
 
-       /* Disable AXI interface */
+       /* Disable AXI interface by asserting FPGA resets */
        writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
 
        /* Set Level Shifters DT618760 */
@@ -99,7 +99,7 @@ void zynq_slcr_devcfg_enable(void)
        /* Set Level Shifters DT618760 */
        writel(0xF, &slcr_base->lvl_shftr_en);
 
-       /* Disable AXI interface */
+       /* Enable AXI interface by de-asserting FPGA resets */
        writel(0x0, &slcr_base->fpga_rst_ctrl);
 
        zynq_slcr_lock();