imx: clock support enet2 anatop clock support

To i.MX6SX/UL, two ethernet interfaces are supported.
Add ENET2 clock support:
1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed.
   To value 1, only i.MX6SX/UL can pass the check.
2. Modify board code who use this api to follow new api prototype.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 9cf4eece137ee0657aecc5284ddd6f4bb198f403..ba6cc75a7b21193e51f5d17e651c1a3a61afda1c 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -524,7 +524,7 @@ void enable_qspi_clk(int qspi_num)
 #endif
 
 #ifdef CONFIG_FEC_MXC
-int enable_fec_anatop_clock(enum enet_freq freq)
+int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 {
        u32 reg = 0;
        s32 timeout = 100000;
@@ -535,9 +535,19 @@ int enable_fec_anatop_clock(enum enet_freq freq)
        if (freq < ENET_25MHZ || freq > ENET_125MHZ)
                return -EINVAL;
 
-       reg = readl(&anatop->pll_enet);
-       reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
-       reg |= freq;
+       if (fec_id == 0) {
+               reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
+               reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
+       } else if (fec_id == 1) {
+               /* Only i.MX6SX/UL support ENET2 */
+               if (!(is_cpu_type(MXC_CPU_MX6SX) ||
+                     is_cpu_type(MXC_CPU_MX6UL)))
+                       return -EINVAL;
+               reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
+               reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
+       } else {
+               return -EINVAL;
+       }
 
        if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
            (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
@@ -552,7 +562,10 @@ int enable_fec_anatop_clock(enum enet_freq freq)
        }
 
        /* Enable FEC clock */
-       reg |= BM_ANADIG_PLL_ENET_ENABLE;
+       if (fec_id == 0)
+               reg |= BM_ANADIG_PLL_ENET_ENABLE;
+       else
+               reg |= BM_ANADIG_PLL_ENET2_ENABLE;
        reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
        writel(reg, &anatop->pll_enet);
 

diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 7b3bbb8185b0d511afe368770acd812257c55d77..2b220d6f8f97d30d2054388351c828a6d7362a74 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -64,7 +64,7 @@ int enable_pcie_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
-int enable_fec_anatop_clock(enum enet_freq freq);
+int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);
 void enable_qspi_clk(int qspi_num);
 void enable_thermal_clk(void);

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index fe75da4c98900ffddf35b419cb2f4fc174f1ee99..10306cd776c2f85bf73bcd08ac53c681f8f0aca3 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -1052,6 +1052,12 @@ struct mxc_ccm_reg {
 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v)  \
        (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
 
+/* ENET2 for i.MX6SX/UL */
+#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
+#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C
+#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v)  \
+       (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
+
 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
 #define BP_ANADIG_PFD_480_PFD3_FRAC      24

diff --git a/board/aristainetos/aristainetos-v1.c b/board/aristainetos/aristainetos-v1.c
index d6a761430d9a6a68ecf0e4d9482ca248ecd268c8..b8fed2e3fdccaccd02b8f098688929cd30de1e2d 100644 (file)
--- a/board/aristainetos/aristainetos-v1.c
+++ b/board/aristainetos/aristainetos-v1.c
@@ -185,7 +185,7 @@ int board_eth_init(bd_t *bis)
        /* clear gpr1[14], gpr1[18:17] to select anatop clock */
        clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
 
-       ret = enable_fec_anatop_clock(ENET_50MHZ);
+       ret = enable_fec_anatop_clock(0, ENET_50MHZ);
        if (ret)
                return ret;
 

diff --git a/board/barco/platinum/platinum_picon.c b/board/barco/platinum/platinum_picon.c
index b2eab766c5872fb74989412a6a9d8abad4bcac44..0384a26e925b5b83565c552ecbb6c342d32cba95 100644 (file)
--- a/board/barco/platinum/platinum_picon.c
+++ b/board/barco/platinum/platinum_picon.c
@@ -148,7 +148,7 @@ int platinum_setup_enet(void)
        /* set GPIO_16 as ENET_REF_CLK_OUT */
        setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 
-       return enable_fec_anatop_clock(ENET_50MHZ);
+       return enable_fec_anatop_clock(0, ENET_50MHZ);
 }
 
 int platinum_setup_i2c(void)

diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 98602f889ec67fdfd1678851b546ebd983f849f9..7c0e90ad0bc0f866b1c32fde76866e385523ee24 100644 (file)
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -361,7 +361,7 @@ static void setup_fec(void)
                 * select ENET MAC0 TX clock from PLL
                 */
                imx_iomux_set_gpr_register(5, 9, 1, 1);
-               enable_fec_anatop_clock(ENET_125MHZ);
+               enable_fec_anatop_clock(0, ENET_125MHZ);
        }
 
        setup_iomux_enet();

diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 7c18c90bce9eb96275fab8ae6cd30fc2fcfd6593..98e3ef0489ebb51b66773ff8e66351c2093f7664 100644 (file)
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -279,7 +279,7 @@ static int setup_fec(void)
        /* clear gpr1[14], gpr1[18:17] to select anatop clock */
        clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
 
-       return enable_fec_anatop_clock(ENET_50MHZ);
+       return enable_fec_anatop_clock(0, ENET_50MHZ);
 }
 #endif
 

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index d58a79a6b8dff1a4c4b9463f33cfb54bf48b8636..ffc0046fb9a78ce0c0d83e1e1f30cb51f10b432a 100644 (file)
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -170,7 +170,7 @@ static int setup_fec(void)
        reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
        writel(reg, &anatop->pll_enet);
 
-       return enable_fec_anatop_clock(ENET_125MHZ);
+       return enable_fec_anatop_clock(0, ENET_125MHZ);
 }
 
 int board_eth_init(bd_t *bis)

diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 9b1ecf0457d49d3cdeac07102a8ba3256282cdc8..8247e4368a4c4ef8501858802948a14d12db98c9 100644 (file)
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -164,7 +164,7 @@ int board_eth_init(bd_t *bis)
        struct mii_dev *bus;
        struct phy_device *phydev;
 
-       int ret = enable_fec_anatop_clock(ENET_25MHZ);
+       int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
        if (ret)
                return ret;