Add and fix DRAM register defines and two func prototypes in common QC/A header

diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h
index 204f720d749424425db4dcab1863307573e1e348..30c650100b6f7058b3b4346da5571900c68a2deb 100644 (file)
--- a/u-boot/include/soc/qca_soc_common.h
+++ b/u-boot/include/soc/qca_soc_common.h
@@ -121,22 +121,22 @@
 #define QCA_DDR_CFG_TMRD_MASK                                  BITS(QCA_DDR_CFG_TMRD_SHIFT, 4)
 #define QCA_DDR_CFG_CAS_3LSB_SHIFT                             27
 #define QCA_DDR_CFG_CAS_3LSB_MASK                              BITS(QCA_DDR_CFG_CAS_3LSB_SHIFT, 3)
-#define QCA_DDR_CFG_OPEN_PAGE_SHIFT                            30
-#define QCA_DDR_CFG_OPEN_PAGE_MASK                             1 << QCA_DDR_CFG_OPEN_PAGE_SHIFT
+#define QCA_DDR_CFG_PAGE_CLOSE_SHIFT                   30
+#define QCA_DDR_CFG_PAGE_CLOSE_MASK                            (1 << QCA_DDR_CFG_PAGE_CLOSE_SHIFT)
 #define QCA_DDR_CFG_CAS_MSB_SHIFT                              31
-#define QCA_DDR_CFG_CAS_MSB_MASK                               1 << QCA_DDR_CFG_CAS_MSB_SHIFT
+#define QCA_DDR_CFG_CAS_MSB_MASK                               (1 << QCA_DDR_CFG_CAS_MSB_SHIFT)
 
 /* DDR_CONFIG2 register (DDR DRAM configuration 2) */
 #define QCA_DDR_CFG2_BURST_LEN_SHIFT                   0
 #define QCA_DDR_CFG2_BURST_LEN_MASK                            BITS(QCA_DDR_CFG2_BURST_LEN_SHIFT, 4)
 #define QCA_DDR_CFG2_BURST_TYPE_SHIFT                  4
-#define QCA_DDR_CFG2_BURST_TYPE_MASK                   1 << QCA_DDR_CFG2_BURST_TYPE_SHIFT
+#define QCA_DDR_CFG2_BURST_TYPE_MASK                   (1 << QCA_DDR_CFG2_BURST_TYPE_SHIFT)
 #define QCA_DDR_CFG2_CTRL_OE_EN_SHIFT                  5
-#define QCA_DDR_CFG2_CTRL_OE_EN_MASK                   1 << QCA_DDR_CFG2_CTRL_OE_EN_SHIFT
+#define QCA_DDR_CFG2_CTRL_OE_EN_MASK                   (1 << QCA_DDR_CFG2_CTRL_OE_EN_SHIFT)
 #define QCA_DDR_CFG2_PHASE_SEL_SHIFT                   6
-#define QCA_DDR_CFG2_PHASE_SEL_MASK                            1 << QCA_DDR_CFG2_PHASE_SEL_SHIFT
+#define QCA_DDR_CFG2_PHASE_SEL_MASK                            (1 << QCA_DDR_CFG2_PHASE_SEL_SHIFT)
 #define QCA_DDR_CFG2_CKE_SHIFT                                 7
-#define QCA_DDR_CFG2_CKE_MASK                                  1 << QCA_DDR_CFG2_CKE_SHIFT
+#define QCA_DDR_CFG2_CKE_MASK                                  (1 << QCA_DDR_CFG2_CKE_SHIFT)
 #define QCA_DDR_CFG2_TWR_SHIFT                                 8
 #define QCA_DDR_CFG2_TWR_MASK                                  BITS(QCA_DDR_CFG2_TWR_SHIFT, 4)
 #define QCA_DDR_CFG2_TRTW_SHIFT                                        12
@@ -148,9 +148,9 @@
 #define QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT   26
 #define QCA_DDR_CFG2_GATE_OPEN_LATENCY_MASK            BITS(QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT, 4)
 #define QCA_DDR_CFG2_SWAP_A26_A27_SHIFT                        30
-#define QCA_DDR_CFG2_SWAP_A26_A27_MASK                 1 << QCA_DDR_CFG2_SWAP_A26_A27_SHIFT
+#define QCA_DDR_CFG2_SWAP_A26_A27_MASK                 (1 << QCA_DDR_CFG2_SWAP_A26_A27_SHIFT)
 #define QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT              31
-#define QCA_DDR_CFG2_HALF_WIDTH_LOW_MASK               1 << QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT
+#define QCA_DDR_CFG2_HALF_WIDTH_LOW_MASK               (1 << QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT)
 
 /* DDR_MODE register (DDR mode register value) */
 #define QCA_DDR_MR_VALUE_SHIFT                                 0
@@ -163,23 +163,23 @@
 
 /* DDR_CONTROL register (DDR control) */
 #define QCA_DDR_CTRL_FORCE_MRS_SHIFT                   0
-#define QCA_DDR_CTRL_FORCE_MRS_MASK                            1 << QCA_DDR_CTRL_FORCE_MRS_SHIFT
+#define QCA_DDR_CTRL_FORCE_MRS_MASK                            (1 << QCA_DDR_CTRL_FORCE_MRS_SHIFT)
 #define QCA_DDR_CTRL_FORCE_EMRS_SHIFT                  1
-#define QCA_DDR_CTRL_FORCE_EMRS_MASK                   1 << QCA_DDR_CTRL_FORCE_EMRS_SHIFT
+#define QCA_DDR_CTRL_FORCE_EMRS_MASK                   (1 << QCA_DDR_CTRL_FORCE_EMRS_SHIFT)
 #define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT  2
-#define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_MASK   1 << QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT
+#define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_MASK   (1 << QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT)
 #define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT 3
-#define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_MASK  1 << QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT
+#define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_MASK  (1 << QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT)
 #define QCA_DDR_CTRL_FORCE_EMR2S_SHIFT                 4
-#define QCA_DDR_CTRL_FORCE_EMR2S_MASK                  1 << QCA_DDR_CTRL_FORCE_EMR2S_SHIFT
+#define QCA_DDR_CTRL_FORCE_EMR2S_MASK                  (1 << QCA_DDR_CTRL_FORCE_EMR2S_SHIFT)
 #define QCA_DDR_CTRL_FORCE_EMR3S_SHIFT                 5
-#define QCA_DDR_CTRL_FORCE_EMR3S_MASK                  1 << QCA_DDR_CTRL_FORCE_EMR3S_SHIFT
+#define QCA_DDR_CTRL_FORCE_EMR3S_MASK                  (1 << QCA_DDR_CTRL_FORCE_EMR3S_SHIFT)
 
 /* DDR_REFRESH register (DDR refresh control and configuration) */
 #define QCA_DDR_REFRESH_PERIOD_SHIFT                   0
 #define QCA_DDR_REFRESH_PERIOD_MASK                            BITS(QCA_DDR_REFRESH_PERIOD_SHIFT, 14)
 #define QCA_DDR_REFRESH_EN_SHIFT                               14
-#define QCA_DDR_REFRESH_EN_MASK                                        1 << QCA_DDR_REFRESH_EN_SHIFT
+#define QCA_DDR_REFRESH_EN_MASK                                        (1 << QCA_DDR_REFRESH_EN_SHIFT)
 
 /* DDR_RD_DATA_THIS_CYCLE register (DDR read data capture bit mask) */
 #define QCA_DDR_RD_DATA_THIS_CYCLE_VEC_SHIFT   0
@@ -201,7 +201,7 @@
 
 /* DDR_DDR2_CONFIG register (DDR2 configuration) */
 #define QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT                 0
-#define QCA_DDR_DDR2_CFG_DDR2_EN_MASK                  1 << QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT
+#define QCA_DDR_DDR2_CFG_DDR2_EN_MASK                  (1 << QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT)
 #define QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT               2
 #define QCA_DDR_DDR2_CFG_DDR2_TFAW_MASK                        BITS(QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT, 6)
 #if (SOC_TYPE & QCA_AR933X_SOC)
@@ -212,6 +212,28 @@
        #define QCA_DDR_DDR2_CFG_DDR2_TWL_MASK          BITS(QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT, 4)
 #endif
 
+/* DDR_CTRL_CFG (DDR controller configuration) */
+#define QCA_DDR_CTRL_CFG_SDRAM_EN_SHIFT                        0
+#define QCA_DDR_CTRL_CFG_SDRAM_EN_MASK                 (1 << QCA_DDR_CTRL_CFG_SDRAM_EN_SHIFT)
+#define QCA_DDR_CTRL_CFG_HALF_WIDTH_SHIFT              1
+#define QCA_DDR_CTRL_CFG_HALF_WIDTH_MASK               (1 << QCA_DDR_CTRL_CFG_HALF_WIDTH_SHIFT)
+#define QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_SHIFT            2
+#define QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_MASK             (1 << QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_SHIFT)
+#define QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_SHIFT            3
+#define QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_MASK             (1 << QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_SHIFT)
+#define QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_SHIFT   4
+#define QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_MASK            (1 << QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_SHIFT)
+#define QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_SHIFT            6
+#define QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_MASK             (1 << QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_SHIFT)
+
+/* DDR_CONFIG3 register (DDR DRAM configuration 3) */
+#define QCA_DDR_CFG3_TRFC_LSB_SHIFT                            0
+#define QCA_DDR_CFG3_TRFC_LSB_MASK                             BITS(QCA_DDR_CFG3_TRFC_LSB_SHIFT, 2)
+#define QCA_DDR_CFG3_TRAS_MSB_SHIFT                            2
+#define QCA_DDR_CFG3_TRAS_MSB_MASK                             (1 << QCA_DDR_CFG3_TRAS_MSB_SHIFT)
+#define QCA_DDR_CFG3_TWR_MSB_SHIFT                             3
+#define QCA_DDR_CFG3_TWR_MSB_MASK                              (1 << QCA_DDR_CFG3_TWR_MSB_SHIFT)
+
 /*
  * Low-Speed UART registers
  */
@@ -1504,6 +1526,8 @@ u32    qca_sf_sfdp_info(u32 bank, u32 *flash_size, u32 *sector_size, u8 *erase_c
 u32    qca_sf_jedec_id(u32 bank);
 u32    qca_dram_type(void);
 u32    qca_dram_size(void);
+u32    qca_dram_cas_lat(void);
+u32    qca_dram_ddr_width(void);
 void   qca_dram_init(void);
 #endif /* !__ASSEMBLY__ */