},
{
/* Tested! */
- 500, 500, 250, 25,
- _ar933x_spi_ctrl_addr_reg_val(10, 1, 0),
+ 410, 410, 205, 25,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
{
- _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1),
+ _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1),
_ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
- _ar933x_cpu_pll_dither_frac_reg_val(0)
+ _ar933x_cpu_pll_dither_frac_reg_val(820)
}, {
- _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1),
+ _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1),
_ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
- _ar933x_cpu_pll_dither_frac_reg_val(0)
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
},
},
- #else
{
- 25, 25, 12, 1,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
- {
- _qca95xx_cpu_pll_cfg_reg_val(1, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(1, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
- }, {
- _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(4, 4, 8, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
- },
- }, {
- 25, 25, 25, 3,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ /* Tested! */
+ 420, 420, 210, 26,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(1, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(1, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(33, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(615)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(4, 4, 4, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(21, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
},
- }, {
- 50, 50, 25, 3,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ },
+ {
+ /* Tested! */
+ 430, 430, 215, 26,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(2, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(34, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(410)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(21, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
},
- }, {
- 50, 50, 50, 6,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ },
+ {
+ /* Tested! */
+ 440, 440, 220, 27,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(2, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(35, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(205)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(22, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
},
- }, {
- 75, 75, 25, 3,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ },
+ {
+ /* Tested! */
+ 450, 450, 225, 28,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(36, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(45, 2, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
},
- }, {
- 75, 75, 50, 6,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ },
+ {
+ /* Tested! */
+ 460, 460, 230, 28,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(36, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(820)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(23, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
},
- }, {
- 75, 75, 75, 9,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ },
+ {
+ /* Tested! */
+ 470, 470, 235, 29,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(37, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(615)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(23, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
},
- }, {
- 100, 100, 25, 3,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ },
+ {
+ /* Tested! */
+ 480, 480, 240, 30,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(38, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(410)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
},
- }, {
- 100, 100, 50, 6,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ },
+ {
+ /* Tested! */
+ 490, 490, 245, 30,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(39, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(205)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
},
- }, {
- 100, 100, 100, 12,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ },
+ {
+ /* Tested! */
+ 500, 500, 250, 25,
+ _ar933x_spi_ctrl_addr_reg_val(10, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
},
- }, {
- 125, 50, 25, 3,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ },
+ {
+ /* Tested! */
+ 510, 510, 255, 25,
+ _ar933x_spi_ctrl_addr_reg_val(10, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(820)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
},
- }, {
- 125, 50, 50, 6,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ },
+ {
+ /* Tested! */
+ 520, 520, 260, 26,
+ _ar933x_spi_ctrl_addr_reg_val(10, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(41, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(615)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(26, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
},
- }, {
- 125, 62, 25, 3,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ },
+ {
+ /* Tested! */
+ 530, 265, 132, 22,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 5, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(42, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(410)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 10, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(26, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
},
- }, {
- 125, 62, 50, 6,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ },
+ {
+ /* Tested! */
+ 540, 270, 135, 22,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(43, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(205)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 2, 1, 0, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(27, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
},
- }, {
- 125, 62, 62, 7,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ },
+ {
+ /* Tested! */
+ 550, 275, 137, 22,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(44, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 4, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(27, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
},
- }, {
- 125, 100, 25, 3,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ },
+ {
+ /* Tested! */
+ 560, 280, 140, 23,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(44, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(820)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 4, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
},
- }, {
- 125, 100, 50, 6,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ },
+ {
+ /* Tested! */
+ 570, 285, 142, 23,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(45, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(615)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 2, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
},
- }, {
- 125, 100, 62, 7,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ },
+ {
+ /* Tested! */
+ 580, 290, 145, 24,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
{
- _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _ar933x_cpu_pll_cfg_reg_val(46, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(410)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 2, 1, 1, 0),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
- },
- }, {
- 125, 100, 100, 12,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ _ar933x_cpu_pll_cfg_reg_val(29, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ #else
+ {
+ /* Tested! */
+ 100, 100, 100, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(4, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(28, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(28, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(7, 7, 7, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(35, 2, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(35, 2, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(7, 7, 7, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
- 150, 150, 75, 9,
- _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ /* Tested! */
+ 125, 100, 100, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(4, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(25, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(28, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 7, 7, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(35, 2, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 7, 7, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(16),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
150, 150, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 1, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 1, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 1, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 1, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
- 150, 150, 150, 18,
+ /* Tested! */
+ 150, 150, 150, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 1, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 1, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 1, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 1, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
160, 160, 80, 10,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 1, 0),
- _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 1, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 1, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 0, 1, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
170, 170, 85, 10,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
180, 180, 90, 11,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
200, 200, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 6, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 6, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
- }
+ },
}, {
+ /* Tested! */
200, 200, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
- }
+ },
}, {
+ /* Tested! */
200, 200, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 3, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 3, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
- }
+ },
}, {
+ /* Tested! */
300, 200, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 6, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 6, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
- }
+ },
}, {
+ /* Tested! */
300, 200, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
- }
+ },
}, {
+ /* Tested! */
300, 200, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 3, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 3, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
- }
+ },
}, {
+ /* Tested! */
300, 300, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
- }
+ },
}, {
+ /* Tested! */
300, 300, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
300, 300, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
350, 350, 175, 21,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
360, 360, 180, 22,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
380, 380, 190, 23,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(46, 3, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(46, 3, 1, 0, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
- _qca95xx_cpu_pll_dither_reg_val(0),
- _qca95xx_ddr_pll_dither_reg_val(0)
+ _qca95xx_cpu_pll_dither_reg_val(13),
+ _qca95xx_ddr_pll_dither_reg_val(205)
}, {
_qca95xx_cpu_pll_cfg_reg_val(19, 1, 0, 1, 0),
_qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 1, 0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
400, 200, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
_qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
400, 200, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
_qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
400, 200, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
_qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
400, 300, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
400, 300, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
400, 300, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
400, 300, 300, 25,
_qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
400, 400, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
400, 400, 300, 25,
_qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
500, 200, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
_qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
500, 200, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
500, 200, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
_qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
500, 300, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
500, 300, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
500, 300, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
500, 300, 250, 25,
_qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
500, 300, 300, 25,
_qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
500, 400, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
500, 400, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
500, 400, 250, 25,
_qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
500, 500, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
500, 500, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
500, 500, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
_qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
500, 500, 250, 25,
_qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
500, 500, 300, 25,
_qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
550, 200, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
550, 200, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
550, 200, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
_qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
550, 300, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
550, 300, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
550, 300, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
550, 300, 275, 27,
_qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
550, 300, 300, 25,
_qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
550, 375, 250, 25,
_qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
550, 400, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
560, 450, 225, 28,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 200, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
_qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 200, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 0),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
_qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 0),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 200, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
_qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 300, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 0, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
_qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 0, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 300, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 300, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
_qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 300, 250, 25,
_qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 300, 300, 25,
_qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 400, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 400, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 400, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 400, 300, 25,
_qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 450, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 450, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 450, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 450, 225, 28,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 450, 300, 25,
_qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 500, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 500, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 500, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 500, 250, 25,
_qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 500, 300, 25,
_qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
{
_qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
_qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
_qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
_qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 550, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 550, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 550, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 550, 275, 27,
_qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 550, 300, 25,
_qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 600, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 600, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 600, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 600, 250, 25,
_qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
600, 600, 300, 25,
_qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 200, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(52),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
_qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 200, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 200, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(52),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
_qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
- _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
- _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 300, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 300, 150, 18,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 300, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 300, 300, 25,
_qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 400, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 400, 155, 19,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 400, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 400, 310, 25,
_qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 500, 100, 12,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
_qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(52),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0),
_qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 500, 155, 19,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
_qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
_qca95xx_cpu_pll_dither_reg_val(52),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0),
_qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 500, 166, 20,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
_qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(52),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0),
_qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 500, 206, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
_qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
_qca95xx_cpu_pll_dither_reg_val(52),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0),
_qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 500, 250, 25,
_qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
_qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(52),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0),
_qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
620, 500, 310, 25,
_qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
{
- _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
_qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
_qca95xx_cpu_pll_dither_reg_val(52),
_qca95xx_ddr_pll_dither_reg_val(0)
}, {
- _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0),
_qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
_qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
_qca95xx_cpu_pll_dither_reg_val(0),
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
650, 400, 200, 25,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
650, 420, 210, 26,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
_qca95xx_ddr_pll_dither_reg_val(0)
},
}, {
+ /* Tested! */
650, 450, 225, 28,
_qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
{
* PLL configuration preset list
* =============================
*/
-#if (CONFIG_QCA_PLL == QCA_PLL_PRESET_25_25_12)
+#if (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(1, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(1, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(4, 4, 8, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(28, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(28, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(7, 7, 7, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_25_25_25)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(1, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(1, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(35, 2, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(35, 2, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(7, 7, 7, 1, 1, 1)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(4, 4, 4, 1, 1, 1)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_50_50_25)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(2, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(4, 1, 0, 2)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_50_50_50)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(2, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_100_100) /* Tested! */
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_75_75_25)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(25, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(28, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 7, 7, 1, 1, 1)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(35, 2, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 7, 7, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_cpu_pll_dither_reg_val(16)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1)
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(4, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_75_75_50)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_100) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 1, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 1, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 1, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 1, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_75_75_75)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_150) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 1, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 1, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_25)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_50)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_50_25)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_50_50)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_62_25)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 5, 1, 1, 1)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 10, 1, 1, 1)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_62_50)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 2, 1, 0, 1)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_62_62)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 4, 1, 1, 1)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_100_25)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 4, 1, 1, 1)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_100_50)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 2, 1, 1, 1)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_100_62)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 4, 1, 1, 0)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_100_100)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 1, 1, 1, 1)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_75)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_100)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1)
-
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_150)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
-
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 1, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 1, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 1, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(26, 1, 0, 1, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 1, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_170_170_85)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_170_170_85) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(34, 1, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(34, 1, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(17, 1, 0, 1, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_180_180_90)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_180_180_90) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 1, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 1, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_100) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 6, 1, 1, 1)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 6, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_150) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 4, 1, 1, 1)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_200) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 3, 1, 1, 1)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 3, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_100) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 6, 1, 1, 1)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 6, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_150) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 4, 1, 1, 1)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_200) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 3, 1, 1, 1)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 3, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_100) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_150) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_200) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_350_350_175)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_350_350_175) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(14, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(14, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(35, 4, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_360_360_180)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_360_360_180) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_380_380_190)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_380_380_190) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(46, 3, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(46, 3, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(13)
+ #define QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_ddr_pll_dither_reg_val(205)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(19, 1, 0, 1, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 1, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_300)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_300) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_300)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_300) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_250)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_250) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_300)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_300) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_250)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_250) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_250)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_250) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_300)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_300) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_275)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_275) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_300)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_300) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_375_250)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_375_250) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(30, 1, 0, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_400_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_400_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_560_450_225)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_560_450_225) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 0)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 0, 1)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 0, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_250)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_250) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_300)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_300) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_300)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_300) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_225)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_225) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_300)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_300) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_250)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_250) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_300)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_300) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_275)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_275) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_300)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_300) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_250)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_250) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_300)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_300) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
- #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0)
- #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_300)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_300) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_155)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_155) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_310)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_310) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_100) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1)
#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_155)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_155) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_166)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_166) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_206)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_206) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_250)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_250) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_310)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_310) /* Tested! */
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
#define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_400_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_400_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_cpu_pll_dither_reg_val(16)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_420_210)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_420_210) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_cpu_pll_dither_reg_val(16)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_450_225)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_450_225) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0)
#define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
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