board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config
authorPrabhakar Kushwaha <prabhakar@freescale.com>
Sat, 8 Mar 2014 11:15:04 +0000 (16:45 +0530)
committerYork Sun <yorksun@freescale.com>
Wed, 23 Apr 2014 00:58:47 +0000 (17:58 -0700)
The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher
than 2.5 MHZ.  It violates the IEEE specs.

So Slow MDC clock to comply IEEE specs

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
board/freescale/b4860qds/b4_pbi.cfg

index 57b726eead82de1794091602445a068e8f8d51bf..05377bac5bb248fd6706cbec1ec91f31720053e0 100644 (file)
@@ -22,6 +22,9 @@
 09110024 00100008
 09110028 00100008
 0911002c 00100008
+#slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
 #Flush PBL data
 09138000 00000000
 091380c0 00000000