+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2007
- * Kenati Technologies, Inc.
- *
- * board/ms7722se/lowlevel_init.S
- */
-
-#include <config.h>
-
-#include <asm/processor.h>
-#include <asm/macro.h>
-
-/*
- * Board specific low level init code, called _very_ early in the
- * startup sequence. Relocation to SDRAM has not happened yet, no
- * stack is available, bss section has not been initialised, etc.
- *
- * (Note: As no stack is available, no subroutines can be called...).
- */
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
-
- /*
- * Cache Control Register
- * Instruction Cache Invalidate
- */
- write32 CCR_A, CCR_D
-
- /*
- * Address of MMU Control Register
- * TI == TLB Invalidate bit
- */
- write32 MMUCR_A, MMUCR_D
-
- /* Address of Power Control Register 0 */
- write32 MSTPCR0_A, MSTPCR0_D
-
- /* Address of Power Control Register 2 */
- write32 MSTPCR2_A, MSTPCR2_D
-
- write16 SBSCR_A, SBSCR_D
-
- write16 PSCR_A, PSCR_D
-
- /* 0xA4520004 (Watchdog Control / Status Register) */
-! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */
-
- /* 0xA4520000 (Watchdog Count Register) */
- write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */
-
- /* 0xA4520004 (Watchdog Control / Status Register) */
- write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */
-
- /* 0xA4150000 Frequency control register */
- write32 FRQCR_A, FRQCR_D
-
- write32 CCR_A, CCR_D_2
-
-bsc_init:
-
- write16 PSELA_A, PSELA_D
-
- write16 DRVCR_A, DRVCR_D
-
- write16 PCCR_A, PCCR_D
-
- write16 PECR_A, PECR_D
-
- write16 PJCR_A, PJCR_D
-
- write16 PXCR_A, PXCR_D
-
- write32 CMNCR_A, CMNCR_D
-
- write32 CS0BCR_A, CS0BCR_D
-
- write32 CS2BCR_A, CS2BCR_D
-
- write32 CS4BCR_A, CS4BCR_D
-
- write32 CS5ABCR_A, CS5ABCR_D
-
- write32 CS5BBCR_A, CS5BBCR_D
-
- write32 CS6ABCR_A, CS6ABCR_D
-
- write32 CS0WCR_A, CS0WCR_D
-
- write32 CS2WCR_A, CS2WCR_D
-
- write32 CS4WCR_A, CS4WCR_D
-
- write32 CS5AWCR_A, CS5AWCR_D
-
- write32 CS5BWCR_A, CS5BWCR_D
-
- write32 CS6AWCR_A, CS6AWCR_D
-
- ! SDRAM initialization
- write32 SDCR_A, SDCR_D
-
- write32 SDWCR_A, SDWCR_D
-
- write32 SDPCR_A, SDPCR_D
-
- write32 RTCOR_A, RTCOR_D
-
- write32 RTCSR_A, RTCSR_D
-
- write8 SDMR3_A, SDMR3_D
-
- ! BL bit off (init = ON) (?!?)
-
- stc sr, r0 ! BL bit off(init=ON)
- mov.l SR_MASK_D, r1
- and r1, r0
- ldc r0, sr
-
- rts
- mov #0, r0
-
- .align 2
-
-CCR_A: .long CCR
-MMUCR_A: .long MMUCR
-MSTPCR0_A: .long MSTPCR0
-MSTPCR2_A: .long MSTPCR2
-SBSCR_A: .long SBSCR
-PSCR_A: .long PSCR
-RWTCSR_A: .long RWTCSR
-RWTCNT_A: .long RWTCNT
-FRQCR_A: .long FRQCR
-
-CCR_D: .long 0x00000800
-CCR_D_2: .long 0x00000103
-MMUCR_D: .long 0x00000004
-MSTPCR0_D: .long 0x00001001
-MSTPCR2_D: .long 0xffffffff
-FRQCR_D: .long 0x07022538
-
-PSELA_A: .long 0xa405014E
-PSELA_D: .word 0x0A10
- .align 2
-
-DRVCR_A: .long 0xa405018A
-DRVCR_D: .word 0x0554
- .align 2
-
-PCCR_A: .long 0xa4050104
-PCCR_D: .word 0x8800
- .align 2
-
-PECR_A: .long 0xa4050108
-PECR_D: .word 0x0000
- .align 2
-
-PJCR_A: .long 0xa4050110
-PJCR_D: .word 0x1000
- .align 2
-
-PXCR_A: .long 0xa4050148
-PXCR_D: .word 0x0AAA
- .align 2
-
-CMNCR_A: .long CMNCR
-CMNCR_D: .long 0x00000013
-CS0BCR_A: .long CS0BCR ! Flash bank 1
-CS0BCR_D: .long 0x24920400
-CS2BCR_A: .long CS2BCR ! SRAM
-CS2BCR_D: .long 0x24920400
-CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot
-CS4BCR_D: .long 0x24920400
-CS5ABCR_A: .long CS5ABCR ! Ext slot
-CS5ABCR_D: .long 0x24920400
-CS5BBCR_A: .long CS5BBCR ! USB controller
-CS5BBCR_D: .long 0x24920400
-CS6ABCR_A: .long CS6ABCR ! Ethernet
-CS6ABCR_D: .long 0x24920400
-
-CS0WCR_A: .long CS0WCR
-CS0WCR_D: .long 0x00000300
-CS2WCR_A: .long CS2WCR
-CS2WCR_D: .long 0x00000300
-CS4WCR_A: .long CS4WCR
-CS4WCR_D: .long 0x00000300
-CS5AWCR_A: .long CS5AWCR
-CS5AWCR_D: .long 0x00000300
-CS5BWCR_A: .long CS5BWCR
-CS5BWCR_D: .long 0x00000300
-CS6AWCR_A: .long CS6AWCR
-CS6AWCR_D: .long 0x00000300
-
-SDCR_A: .long SBSC_SDCR
-SDCR_D: .long 0x00020809
-SDWCR_A: .long SBSC_SDWCR
-SDWCR_D: .long 0x00164d0d
-SDPCR_A: .long SBSC_SDPCR
-SDPCR_D: .long 0x00000087
-RTCOR_A: .long SBSC_RTCOR
-RTCOR_D: .long 0xA55A0034
-RTCSR_A: .long SBSC_RTCSR
-RTCSR_D: .long 0xA55A0010
-SDMR3_A: .long 0xFE500180
-SDMR3_D: .long 0x0
-
- .align 1
-
-SBSCR_D: .word 0x0040
-PSCR_D: .word 0x0000
-RWTCSR_D_1: .word 0xA507
-RWTCSR_D_2: .word 0xA507
-RWTCNT_D: .word 0x5A00
- .align 2
-
-SR_MASK_D: .long 0xEFFFFF0F
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8FFC0000
-CONFIG_TARGET_MS7722SE=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200 root=1f01"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_JFFS2=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Hitachi Solution Engine 7722
- *
- * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#ifndef __MS7722SE_H
-#define __MS7722SE_H
-
-#define CONFIG_CPU_SH7722 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-/* SMC9111 */
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE (0xB8000000)
-
-/* MEMORY */
-#define MS7722SE_SDRAM_BASE (0x8C000000)
-#define MS7722SE_FLASH_BASE_1 (0xA0000000)
-#define MS7722SE_FLASH_BANK_SIZE (8*1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
-
-/* SCIF */
-#define CONFIG_CONS_SCIF0 1
-
-#define CONFIG_SYS_MEMTEST_START (MS7722SE_SDRAM_BASE)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
-
-#undef CONFIG_SYS_MEMTEST_SCRATCH /* Scratch address used by the alternate memory test */
-
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* Enable temporary baudrate change while serial download */
-
-#define CONFIG_SYS_SDRAM_BASE (MS7722SE_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* maybe more, but if so u-boot doesn't know about it... */
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */
-
-#define CONFIG_SYS_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image
- in Flash (NOT run time address in SDRAM) ?!? */
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* FLASH */
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_SYS_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */
-
-#define CONFIG_SYS_MAX_FLASH_SECT 150 /* Max number of sectors on each
- Flash chip */
-
-/* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \
- CONFIG_SYS_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \
- }
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) /* Timeout for Flash erase operations (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) /* Timeout for Flash write operations (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) /* Timeout for Flash set sector lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) /* Timeout for Flash clear lock bit operations (in ms) */
-
-#undef CONFIG_SYS_DIRECT_FLASH_TFTP
-
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_ENV_SECT_SIZE (8 * 1024)
-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-#endif /* __MS7722SE_H */