armv8: fsl-layerscape: Add support of GPIO structure

Layerscape Gen2 SoC supports GPIO registers to control GPIO
signals. Adding support of GPIO structure to access GPIO
registers.

Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 1ff5cac344ad76a65bcc6a27751d643e0b9f77c4..b1950054aa38835a1ae9fe4a73efe244d7e21a68 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -82,6 +82,11 @@
 #define QSPI0_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x00550000)
 #define DSPI1_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x01100000)
 
+#define GPIO1_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x1300000)
+#define GPIO2_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x1310000)
+#define GPIO3_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x1320000)
+#define GPIO4_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x1330000)
+
 #define LPUART_BASE                            (CONFIG_SYS_IMMR + 0x01950000)
 
 #define AHCI_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x02200000)
@@ -591,6 +596,16 @@ struct ccsr_serdes {
        u8      res_19a0[0x2000-0x19a0];        /* from 0x19a0 to 0x1fff */
 };
 
+struct ccsr_gpio {
+       u32     gpdir;
+       u32     gpodr;
+       u32     gpdat;
+       u32     gpier;
+       u32     gpimr;
+       u32     gpicr;
+       u32     gpibe;
+};
+
 /* MMU 500 */
 #define SMMU_SCR0                      (SMMU_BASE + 0x0)
 #define SMMU_SCR1                      (SMMU_BASE + 0x4)