drivers: mmc: omap_hsmmc: Fix IO Buffer on OMAP36xx

On the OMAP36xx/37xx the CONTROL_WKUP_CTRL register has
a field (bit 6) named GPIO_IO_PWRDNZ.  If 0, the IO buffers which
are related to GPIO_126, 127 and 129 are disabled. Some boards may
need this for MMC. After the PBIAS is configured, this bit should
be set high to enable these GPIO pins.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index f200e87a38f95f6f098df1f854f12a151d0169aa..37ee2670372155cb419f857564d754c16ee6c89a 100644 (file)
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -33,6 +33,7 @@ CONFIG_CMD_UBI=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_OMAP36XX_PINS=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 0c0778111593e97a4ab48fe497e0aa3b87a659cd..01d1dbfb1b51675870ccb79bbbfc22ae02c6fb34 100644 (file)
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -131,6 +131,18 @@ config MMC_OMAP_HS
 
          If unsure, say N.
 
+config MMC_OMAP36XX_PINS
+       bool "Enable MMC1 on OMAP36xx/37xx"
+       depends on OMAP34XX && MMC_OMAP_HS
+       help
+         This enables extended-drain in the MMC/SD/SDIO1I/O and
+         GPIO-associated I/O cells (gpio_126, gpio_127, and gpio_129)
+         specific to the OMAP36xx/37xx using MMC1
+
+         If you have a controller with this interface, say Y here.
+
+         If unsure, say N.
+
 config SH_SDHI
        bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
        depends on RMOBILE

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 5bb628d1250aed9c627f5a4d8963611387ceae09..b63ce565f2bf0b5aec21c40e898335ae3918e373 100644 (file)
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -38,6 +38,7 @@
 #include <asm/arch/sys_proto.h>
 #endif
 #include <dm.h>
+#include <asm/arch-omap3/mux.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -102,12 +103,22 @@ static unsigned char mmc_board_init(struct mmc *mmc)
        t2_t *t2_base = (t2_t *)T2_BASE;
        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
        u32 pbias_lite;
+#ifdef CONFIG_MMC_OMAP36XX_PINS
+       u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
+#endif
 
        pbias_lite = readl(&t2_base->pbias_lite);
        pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 #ifdef CONFIG_TARGET_OMAP3_CAIRO
        /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
        pbias_lite &= ~PBIASLITEVMODE0;
+#endif
+#ifdef CONFIG_MMC_OMAP36XX_PINS
+       if (get_cpu_family() == CPU_OMAP36XX) {
+               /* Disable extended drain IO before changing PBIAS */
+               wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
+               writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
+       }
 #endif
        writel(pbias_lite, &t2_base->pbias_lite);
 
@@ -115,6 +126,13 @@ static unsigned char mmc_board_init(struct mmc *mmc)
                PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
                &t2_base->pbias_lite);
 
+#ifdef CONFIG_MMC_OMAP36XX_PINS
+       if (get_cpu_family() == CPU_OMAP36XX)
+               /* Enable extended drain IO after changing PBIAS */
+               writel(wkup_ctrl |
+                               OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
+                               OMAP34XX_CTRL_WKUP_CTRL);
+#endif
        writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
                &t2_base->devconf0);