changes for IDS8247 board support

To get the IDS8247 board working following are done:
 - FCC2 is deactivated
 - FCC1 is activated
 - I2C is activated
 - CFI driver is activated
 - Adapted for use with LIBFDT

Signed-off-by: Sergej Stepanov <Sergej.Stepanov@ids.de>
--

diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c
index 19823a474ed09f1c831cefbd260fab9c6d1e70af..b05424d32b29a2cf3120445dc2d0da2f6bd398ad 100644 (file)
--- a/board/ids8247/ids8247.c
+++ b/board/ids8247/ids8247.c
@@ -25,6 +25,12 @@
 #include <ioports.h>
 #include <mpc8260.h>
 
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <libfdt_env.h>
+#include <fdt_support.h>
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -38,12 +44,12 @@ const iop_conf_t iop_conf_tab[4][32] = {
 
     /* Port A configuration */
     {  /*            conf ppar psor pdir podr pdat */
-       /* PA31 */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 COL */
-       /* PA30 */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 CRS */
-       /* PA29 */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 TXER */
-       /* PA28 */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 TXEN */
-       /* PA27 */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 RXDV */
-       /* PA26 */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 RXER */
+       /* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 COL */
+       /* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 CRS */
+       /* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 TXER */
+       /* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 TXEN */
+       /* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 RXDV */
+       /* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 RXER */
        /* PA25 */ {   0,   0,   0,   0,   1,   0   }, /* 8247_P0 */
 #if defined(CONFIG_SOFT_I2C)
        /* PA24 */ {   1,   0,   0,   0,   1,   1   }, /* I2C_SDA2 */
@@ -53,14 +59,14 @@ const iop_conf_t iop_conf_tab[4][32] = {
        /* PA23 */ {   0,   0,   0,   1,   0,   0   }, /* PA23 */
 #endif
        /* PA22 */ {   0,   0,   0,   0,   1,   0   }, /* SMC2_DCD */
-       /* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TXD3 */
-       /* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TXD2 */
-       /* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TXD1 */
-       /* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TXD0 */
-       /* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RXD0 */
-       /* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RXD1 */
-       /* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RXD2 */
-       /* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RXD3 */
+       /* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD3 */
+       /* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD2 */
+       /* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD1 */
+       /* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD0 */
+       /* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD0 */
+       /* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD1 */
+       /* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD2 */
+       /* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD3 */
        /* PA13 */ {   0,   0,   0,   1,   1,   0   }, /* SMC2_RTS */
        /* PA12 */ {   0,   0,   0,   0,   1,   0   }, /* SMC2_CTS */
        /* PA11 */ {   0,   0,   0,   1,   1,   0   }, /* SMC2_DTR */
@@ -79,20 +85,20 @@ const iop_conf_t iop_conf_tab[4][32] = {
 
     /* Port B configuration */
     {  /*            conf ppar psor pdir podr pdat */
-       /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
-       /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
-       /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
-       /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
-       /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
-       /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
-       /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
-       /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
-       /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
-       /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
-       /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
-       /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
-       /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
-       /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+       /* PB31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+       /* PB30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+       /* PB29 */ {   0,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+       /* PB28 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+       /* PB27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+       /* PB26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+       /* PB25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+       /* PB24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+       /* PB23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+       /* PB22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+       /* PB21 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+       /* PB20 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+       /* PB19 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+       /* PB18 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
        /* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
        /* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
        /* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
@@ -123,8 +129,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
        /* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
        /* PC25 */ {   0,   1,   1,   0,   0,   0   }, /* SYNC_IN */
        /* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
-       /* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
-       /* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+       /* PC23 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
+       /* PC22 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
        /* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
        /* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
        /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
@@ -180,7 +186,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
        /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
        /* PD9  */ {   0,   0,   0,   0,   0,   0   }, /* PD9 */
        /* PD8  */ {   0,   0,   0,   0,   0,   0   }, /* PD8 */
-       /* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* MII_MDIO */
+       /* PD7  */ {   1,   0,   0,   1,   0,   1   }, /* MII_MDIO */
        /* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
        /* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
        /* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
@@ -224,7 +230,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
         * mapped by the controller. That means, that the initial mapping has
         * to be (at least) twice as large as the maximum expected size.
         */
-       maxsize = (1 + (~orx | 0x7fff)) / 2;
+       maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
 
        sdmr_ptr = &memctl->memc_psdmr;
        orx_ptr = &memctl->memc_or2;
@@ -315,4 +321,38 @@ nand_init (void)
        printf ("%4lu MB\n", totlen >>20);
 }
 
-#endif
+#endif /* CFG_CMD_NAND */
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+/*
+ * update "memory" property in the blob
+ */
+void ft_blob_update(void *blob, bd_t *bd)
+{
+       int ret, nodeoffset = 0;
+       ulong memory_data[2] = {0};
+
+       memory_data[0] = cpu_to_be32(bd->bi_memstart);
+       memory_data[1] = cpu_to_be32(bd->bi_memsize);
+
+       nodeoffset = fdt_find_node_by_path (blob, "/memory");
+       if (nodeoffset >= 0) {
+               ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
+                                       sizeof(memory_data));
+       if (ret < 0)
+               printf("ft_blob_update): cannot set /memory/reg "
+                       "property err:%s\n", fdt_strerror(ret));
+       }
+       else {
+               /* memory node is required in dts */
+               printf("ft_blob_update(): cannot find /memory node "
+               "err:%s\n", fdt_strerror(nodeoffset));
+       }
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+       ft_cpu_setup( blob, bd);
+       ft_blob_update(blob, bd);
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */

diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
index 85d2bb3f513f5e25d47c358b3e6f2146f7328fdf..bb87fae8c49cc1d31922f726ef195205a74ef3ec 100644 (file)
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -120,6 +120,17 @@
 
 #define CFG_NS16550_COM1        (CFG_UART_BASE + 0x8000)
 
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT       1
+#define CONFIG_OF_BOARD_SETUP  1
+
+#define OF_CPU "PowerPC,8247@0"
+#define OF_SOC "soc@f0000000"
+#define OF_TBCLK       (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000"
+
+
 /*
  * select ethernet configuration
  *
@@ -133,16 +144,18 @@
 #undef CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 #define        CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 #undef CONFIG_ETHER_NONE               /* define if ether on something else */
-#define        CONFIG_ETHER_INDEX    2         /* which SCC/FCC channel for ethernet */
+#define        CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
+#define CONFIG_ETHER_ON_FCC1
+#define FCC_ENET
 
 /*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
+ * - Rx-CLK is CLK10
+ * - Tx-CLK is CLK9
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK       (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CMXFCR_MASK       (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CFG_CMXFCR_VALUE      (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
 # define CFG_CPMFCR_RAMTYPE    0
 # define CFG_FCC_PSMR          (FCC_PSMR_FDE|FCC_PSMR_LPB)
 
@@ -166,6 +179,8 @@
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_BOOTFILESIZE
 
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR               0x51
 
 /*
  * Command line configuration.
@@ -211,7 +226,10 @@
  */
 #define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 
-
+#define CFG_FLASH_CFI                          /* The flash is CFI compatible  */
+#define CFG_FLASH_CFI_DRIVER                   /* Use common CFI driver        */
+#define CFG_FLASH_BANKS_LIST   { 0xFF800000 }
+#define CFG_MAX_FLASH_BANKS_DETECT     1
 /* What should the base address of the main FLASH be and how big is
  * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk
  * The main FLASH is whichever is connected to *CS0.
@@ -227,7 +245,7 @@
  * FLASH organization
  */
 #define CFG_MAX_FLASH_BANKS    1       /* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT     64      /* max num of sects on one chip */
+#define CFG_MAX_FLASH_SECT     128     /* max num of sects on one chip */
 
 #define CFG_FLASH_ERASE_TOUT   240000  /* Flash Erase Timeout (in ms)  */
 #define CFG_FLASH_WRITE_TOUT   500     /* Flash Write Timeout (in ms)  */
@@ -511,12 +529,12 @@
 */
 #define CFG_OR2    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
                         ORxS_BPD_4                     |\
-                        ORxS_ROWST_PBI0_A10             |\
+                        ORxS_ROWST_PBI0_A9             |\
                         ORxS_NUMR_12)
 
-#define CFG_PSDMR  (PSDMR_SDAM_A13_IS_A5 |\
+#define CFG_PSDMR  (PSDMR_SDAM_A14_IS_A5 |\
                         PSDMR_BSMA_A15_A17           |\
-                        PSDMR_SDA10_PBI0_A11         |\
+                        PSDMR_SDA10_PBI0_A10           |\
                         PSDMR_RFRC_5_CLK               |\
                         PSDMR_PRETOACT_2W              |\
                         PSDMR_ACTTORW_2W               |\