--- /dev/null
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_bus_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ unsigned int i2c_address = 0;
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ if (ctrl_num == 0 && i == 0) {
+ i2c_address = SPD_EEPROM_ADDRESS1;
+ }
+ if (ctrl_num == 0 && i == 1) {
+ i2c_address = SPD_EEPROM_ADDRESS2;
+ }
+ if (ctrl_num == 1 && i == 0) {
+ i2c_address = SPD_EEPROM_ADDRESS3;
+ }
+ if (ctrl_num == 1 && i == 1) {
+ i2c_address = SPD_EEPROM_ADDRESS4;
+ }
+ get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+ }
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 7;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 10;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#undef CONFIG_DDR_DLL /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_NUM_DDR_CONTROLLERS 2
-/* #define CONFIG_DDR_INTERLEAVE 1 */
-#define CACHE_LINE_INTERLEAVING 0x20000000
-#define PAGE_INTERLEAVING 0x21000000
-#define BANK_INTERLEAVING 0x22000000
-#define SUPER_BANK_INTERLEAVING 0x23000000
-
#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
#define CONFIG_ALTIVEC 1
/*
* DDR Setup
*/
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
#define MPC86xx_DDR_SDRAM_CLK_CNTL
-#if defined(CONFIG_SPD_EEPROM)
- /*
- * Determine DDR configuration from I2C interface.
- */
- #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
- #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
- #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
- #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_DIMM_SLOTS_PER_CTLR 2
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/*
+ * I2C addresses of SPD EEPROMs
+ */
+#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
+#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
+#define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
+#define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
+
+
+/*
+ * These are used when DDR doesn't use SPD.
+ */
+#define CFG_SDRAM_SIZE 256 /* DDR is 256MB */
+#define CFG_DDR_CS0_BNDS 0x0000000F
+#define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
+#define CFG_DDR_TIMING_3 0x00000000
+#define CFG_DDR_TIMING_0 0x00260802
+#define CFG_DDR_TIMING_1 0x39357322
+#define CFG_DDR_TIMING_2 0x14904cc8
+#define CFG_DDR_MODE_1 0x00480432
+#define CFG_DDR_MODE_2 0x00000000
+#define CFG_DDR_INTERVAL 0x06090100
+#define CFG_DDR_DATA_INIT 0xdeadbeef
+#define CFG_DDR_CLK_CTRL 0x03800000
+#define CFG_DDR_OCD_CTRL 0x00000000
+#define CFG_DDR_OCD_STATUS 0x00000000
+#define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
+#define CFG_DDR_CONTROL2 0x04400000
+
+/*
+ * FIXME: Not used in fixed_sdram function
+ */
+#define CFG_DDR_MODE 0x00000022
+#define CFG_DDR_CS1_BNDS 0x00000000
+#define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */
+#define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */
+#define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */
+#define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */
-#else
- /*
- * Manually set up DDR1 parameters
- */
-
- #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */
-
- #define CFG_DDR_CS0_BNDS 0x0000000F
- #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
- #define CFG_DDR_EXT_REFRESH 0x00000000
- #define CFG_DDR_TIMING_0 0x00260802
- #define CFG_DDR_TIMING_1 0x39357322
- #define CFG_DDR_TIMING_2 0x14904cc8
- #define CFG_DDR_MODE_1 0x00480432
- #define CFG_DDR_MODE_2 0x00000000
- #define CFG_DDR_INTERVAL 0x06090100
- #define CFG_DDR_DATA_INIT 0xdeadbeef
- #define CFG_DDR_CLK_CTRL 0x03800000
- #define CFG_DDR_OCD_CTRL 0x00000000
- #define CFG_DDR_OCD_STATUS 0x00000000
- #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
- #define CFG_DDR_CONTROL2 0x04400000
-
- /* Not used in fixed_sdram function */
-
- #define CFG_DDR_MODE 0x00000022
- #define CFG_DDR_CS1_BNDS 0x00000000
- #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */
- #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */
- #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */
- #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */
-#endif
#define CONFIG_ID_EEPROM
#define CFG_I2C_EEPROM_NXID
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