arm: socfpga: Add onchip RAM size macro

Add OCRAM size macro for Gen5 and Arria 10.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index 929c413e03922926a31d44d3ef307d3c1cdfdf89..b947cc07291c9cac2e8b85f18fcd01793e9d05e6 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -47,4 +47,6 @@
 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS                0xffd13400
 #define SOCFPGA_NOC_FW_H2F_SCR_OFST            0xffd13500
 
+#define SOCFPGA_PHYS_OCRAM_SIZE                        0x40000
+
 #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
index 2725e9fcc3452be751d4deb179029ae6df181a46..da966fb458367c409679ae4aeb84a854a07c564f 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
@@ -59,4 +59,6 @@
 #define SOCFPGA_DMANONSECURE_ADDRESS   0xffe00000
 #define SOCFPGA_DMASECURE_ADDRESS      0xffe01000
 
+#define SOCFPGA_PHYS_OCRAM_SIZE                0x10000
+
 #endif /* _SOCFPGA_BASE_ADDRS_H_ */