P2020: dts: Added PCIe DT nodes

P2020 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index f20d1fa20d757b5239dad37e0662f8f9afffe19e..f696f35960832cd6175241595ab24687e27320f7 100644 (file)
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -25,3 +25,33 @@
                last-interrupt-source = <255>;
        };
 };
+
+/* PCIe controller base address 0x8000 */
+&pci2 {
+       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+       law_trgt_if = <0>;
+       #address-cells = <3>;
+       #size-cells = <2>;
+       device_type = "pci";
+       bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0x9000 */
+&pci1 {
+       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+       law_trgt_if = <1>;
+       #address-cells = <3>;
+       #size-cells = <2>;
+       device_type = "pci";
+       bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0xa000 */
+&pci0 {
+       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+       law_trgt_if = <2>;
+       #address-cells = <3>;
+       #size-cells = <2>;
+       device_type = "pci";
+       bus-range = <0x0 0xff>;
+};

diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
index 4800b76c1c45489155fbb221a051b50300f1c7e4..08befd4c5934071e49561c27eca75703b03ff6e6 100644 (file)
--- a/arch/powerpc/dts/p2020rdb-pc.dts
+++ b/arch/powerpc/dts/p2020rdb-pc.dts
@@ -18,6 +18,23 @@
        soc: soc@ffe00000 {
                ranges = <0x0 0x0 0xffe00000 0x100000>;
        };
+
+       pci2: pcie@ffe08000 {
+               reg = <0x0 0xffe08000 0x0 0x1000>;      /* registers */
+               status = "disabled";
+       };
+
+       pci1: pcie@ffe09000 {
+               reg = <0x0 0xffe09000 0x0 0x1000>;      /* registers */
+               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000   /* downstream I/O */
+                         0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+       };
+
+       pci0: pcie@ffe0a000 {
+               reg = <0x0 0xffe0a000 0x0 0x1000>;      /* registers */
+               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
+                         0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+       };
 };
 
 /include/ "p2020-post.dtsi"

diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts
index 8323b90e6dbcff5c96b59fd9d77037b736ca71df..04b2519e1a568adbc8f70ed9d102952d73efcc6b 100644 (file)
--- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -18,6 +18,23 @@
        soc: soc@fffe00000 {
                ranges = <0x0 0xf 0xffe00000 0x100000>;
        };
+
+       pci2: pcie@fffe08000 {
+               reg = <0xf 0xffe08000 0x0 0x1000>;      /* registers */
+               status = "disabled";
+       };
+
+       pci1: pcie@fffe09000 {
+               reg = <0xf 0xffe09000 0x0 0x1000>;      /* registers */
+               ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000   /* downstream I/O */
+                         0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+       };
+
+       pci0: pcie@fffe0a000 {
+               reg = <0xf 0xffe0a000 0x0 0x1000>;      /* registers */
+               ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000   /* downstream I/O */
+                         0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+       };
 };
 
 /include/ "p2020-post.dtsi"