obj-y += fsl_epu.o
obj-y += soc.o
-obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
obj-$(CONFIG_SPL) += spl.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/immap_ls102xa.h>
-#include <ahci.h>
-#include <scsi.h>
-
-/* port register default value */
-#define AHCI_PORT_PHY_1_CFG 0xa003fffe
-#define AHCI_PORT_PHY_2_CFG 0x28183414
-#define AHCI_PORT_PHY_3_CFG 0x0e080e06
-#define AHCI_PORT_PHY_4_CFG 0x064a080b
-#define AHCI_PORT_PHY_5_CFG 0x2aa86470
-#define AHCI_PORT_TRANS_CFG 0x08000029
-
-#define SATA_ECC_REG_ADDR 0x20220520
-#define SATA_ECC_DISABLE 0x00020000
-
-int ls1021a_sata_init(void)
-{
- struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
- out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE);
-#endif
-
- out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
- out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
- out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG);
- out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG);
- out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
-
- ahci_init((void __iomem *)AHCI_BASE_ADDR);
- scsi_scan(false);
-
- return 0;
-}
u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
};
-
-
-/* AHCI (sata) register map */
-struct ccsr_ahci {
- u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
- u32 pcfg; /* port config */
- u32 ppcfg; /* port phy1 config */
- u32 pp2c; /* port phy2 config */
- u32 pp3c; /* port phy3 config */
- u32 pp4c; /* port phy4 config */
- u32 pp5c; /* port phy5 config */
- u32 paxic; /* port AXI config */
- u32 axicc; /* AXI cache control */
- u32 axipc; /* AXI PROT control */
- u32 ptc; /* port Trans Config */
- u32 pts; /* port Trans Status */
- u32 plc; /* port link config */
- u32 plc1; /* port link config1 */
- u32 plc2; /* port link config2 */
- u32 pls; /* port link status */
- u32 pls1; /* port link status1 */
- u32 pcmdc; /* port CMD config */
- u32 ppcs; /* port phy control status */
- u32 pberr; /* port 0/1 BIST error */
- u32 cmds; /* port 0/1 CMD status error */
-};
-
#define RCPM_POWMGTCSR 0x130
#define RCPM_POWMGTCSR_SERDES_PW 0x80000000
#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-
-#ifndef __FSL_SATA_H_
-#define __FSL_SATA_H_
-
-int ls1021a_sata_init(void);
-#endif
#include <asm/arch/ls102xa_devdis.h>
#include <asm/arch/ls102xa_soc.h>
-#include <asm/arch/ls102xa_sata.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_immap.h>
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
-#ifdef CONFIG_SCSI_AHCI_PLAT
- ls1021a_sata_init();
-#endif
-
return 0;
}
#endif
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_devdis.h>
-#include <asm/arch/ls102xa_sata.h>
#include <hwconfig.h>
#include <mmc.h>
#include <fsl_csu.h>
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
-#ifdef CONFIG_SCSI_AHCI_PLAT
- ls1021a_sata_init();
-#endif
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
#endif
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_devdis.h>
#include <asm/arch/ls102xa_soc.h>
-#include <asm/arch/ls102xa_sata.h>
#include <hwconfig.h>
#include <mmc.h>
#include <fsl_csu.h>
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
-#ifdef CONFIG_SCSI_AHCI_PLAT
- ls1021a_sata_init();
-#endif
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
#endif