sh: boards: Change clock definition of SCIF and TMU
authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Wed, 21 Aug 2013 07:11:21 +0000 (16:11 +0900)
committerNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Thu, 17 Oct 2013 00:43:36 +0000 (09:43 +0900)
This changes clock definition of SCIF from CONFIG_SYS_CLK_FREQ to
CONFIG_SH_SCIF_CLK_FREQ, and clock definition of TMU from CONFIG_SYS_CLK_FREQ to
CONFIG_SH_TMU_CLK_FREQ for boards.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
20 files changed:
include/configs/MigoR.h
include/configs/ap325rxa.h
include/configs/ap_sh4a_4a.h
include/configs/ecovec.h
include/configs/espt.h
include/configs/mpr2.h
include/configs/ms7720se.h
include/configs/ms7722se.h
include/configs/ms7750se.h
include/configs/r0p7734.h
include/configs/r2dplus.h
include/configs/r7780mp.h
include/configs/rsk7203.h
include/configs/rsk7264.h
include/configs/rsk7269.h
include/configs/sh7752evb.h
include/configs/sh7757lcr.h
include/configs/sh7763rdp.h
include/configs/sh7785lcr.h
include/configs/shmin.h

index dc4a7681be124c67a84aa549280e45937492b153..d536ebdc6dc08c9be186b25c5bbbce81a3b4ddda 100644 (file)
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV         (4)     /* 4 (default), 16, 64, 256 or 1024 */
 #define CONFIG_SYS_HZ          1000
 
index af3a4277e2971c650b019217dcad562c4dde3c61..07ec8a7d538abaa4e579c546802516caa7c61790 100644 (file)
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV         (4)     /* 4 (default), 16, 64, 256 or 1024 */
 #define CONFIG_SYS_HZ          1000
 
index b9112910e7712c9dfbc8294c67a232304124b6f2..ada42d725e9f96010f186528d111680d4a7cf67b 100644 (file)
 #else
 #define CONFIG_SYS_CLK_FREQ 44444444
 #endif
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV      4
 #define CONFIG_SYS_HZ       1000
 
index 2c9594be03fc46e6881862ba82ce4062eecc6a60..34bd0b3ae9455f41220b5864538f2b740bebbce0 100644 (file)
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ 41666666
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV      4
 #define CONFIG_SYS_HZ       1000
 
index e906efbdbaad7daf3a5e8dc0e72578b41c43e946..f1a44bcf5c5ff54dc54d1c16123fb712caa81803 100644 (file)
@@ -98,6 +98,8 @@
 
 /* Clock */
 #define CONFIG_SYS_CLK_FREQ    66666666
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV      4
 #define CONFIG_SYS_HZ       1000
 
index 7e187237236c8213b7bdffc1765b0055e1250f49..b0b23a62801a04c1a8356b9317987c0cd9887674 100644 (file)
@@ -67,6 +67,8 @@
 
 /* Clocks */
 #define CONFIG_SYS_CLK_FREQ    24000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV         4       /* 4 (default), 16, 64, 256 or 1024 */
 #define CONFIG_SYS_HZ          1000
 
index bc8bb8d5a7c04dc378df2451c473610fb815c6f6..d6b17624b6f1dec084cd8f219cd662d28c16c871 100644 (file)
@@ -85,6 +85,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV         4       /* 4 (default), 16, 64, 256 or 1024 */
 #define CONFIG_SYS_HZ          1000
 
index a757737f84e00fbfd216bacb453cab6374185f8f..787c255b772f240c3f0e5f7866a7f4ffefeb59b4 100644 (file)
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV         (4)     /* 4 (default), 16, 64, 256 or 1024 */
 #define CONFIG_SYS_HZ          1000
 
index c4c96bfb2dcadd6d691f3b60f06f80d93ba65dee..37ef02e839f566aac31023cb319487af5bebb7cf 100644 (file)
@@ -82,6 +82,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV         4
 #define CONFIG_SYS_HZ          1000
 
index 080448090dda8b7b29c3a04a12fff6dab73e3d70..5894f5f4a929b8f3de8b29e7291c880cf4d27388 100644 (file)
 #else
 #define CONFIG_SYS_CLK_FREQ 44444444
 #endif
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV      4
 #define CONFIG_SYS_HZ       1000
 
index 65dcffb29be495ea88b83f12a2626cdb803aebdc..8c11b99ea82fa893dfc9727ad3962c256cb66d4c 100644 (file)
@@ -77,6 +77,8 @@
  * SuperH Clock setting
  */
 #define CONFIG_SYS_CLK_FREQ    60000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV         4
 #define CONFIG_SYS_HZ          1000
 #define        CONFIG_SYS_PLL_SETTLING_TIME    100/* in us */
index dd1caf18bc8df5e06248de804f9fd4757d0f63ab..07c9903ec8cb6bf79d7a12c4548758ed74e0c4c6 100644 (file)
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV         4
 #define CONFIG_SYS_HZ          1000
 
index d7473c3e62090a80ce17c9bf78e6dddfa082013b..2e96883da8bbb8e399f87705b635a92f31a055a3 100644 (file)
@@ -85,6 +85,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CMT_CLK_DIVIDER        32      /* 8 (default), 32, 128 or 512 */
 #define CONFIG_SYS_HZ                  (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
 
index 783467af5ea9c533ca1e11d3643f78d5bff0ae48..cf7bc63c96e5183b14227b4acacb02041b31bfad 100644 (file)
@@ -65,6 +65,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    36000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CMT_CLK_DIVIDER                32      /* 8 (default), 32, 128 or 512 */
 #define CONFIG_SYS_HZ          (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
 
index 11c2a93c1a32bcac25c09e8d3c2e90c7c192ed06..1f4e2f3cc6d90466959da692dd3571b56ba0929c 100644 (file)
@@ -64,6 +64,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    66125000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CMT_CLK_DIVIDER                32      /* 8 (default), 32, 128 or 512 */
 #define CONFIG_SYS_HZ          (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
 
index fb4dc6fde422c687c2ce13f4fdfb951ae215b6eb..bab7e4dc8e1c062d9f4bdfc78e00daa89b9b6136 100644 (file)
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    48000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV 4
 #define CONFIG_SYS_HZ          1000
 #endif /* __SH7752EVB_H */
index af76f49dd26770b393f2ebd3b7abb0e32ac89d27..b0df4da87495758d1a3a4cc7ce75ae3ace5968f1 100644 (file)
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    48000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV 4
 #define CONFIG_SYS_HZ          1000
 #endif /* __SH7757LCR_H */
index c1d33d87bab0aca1be740c555c326cafabef83f5..d0dc10240fe1db5652eec8b10718a07d28dfd69e 100644 (file)
@@ -98,6 +98,8 @@
 
 /* Clock */
 #define CONFIG_SYS_CLK_FREQ    66666666
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV         (4)     /* 4 (default), 16, 64, 256 or 1024 */
 #define CONFIG_SYS_HZ          1000
 
index 04f1d2284e751daf5b6279584c5d35d768fe7f5e..baee07b36de7291f72f41329d9f71f09c68c65d1 100644 (file)
 /* Board Clock */
 /* The SCIF used external clock. system clock only used timer. */
 #define CONFIG_SYS_CLK_FREQ    50000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV         4
 #define CONFIG_SYS_HZ          1000
 
index 5fb71760f852b561551643ddb1237d68a3ef1f0d..8cdb8f94d16710be41ec1465b6282f1cf261d28b 100644 (file)
 #else
 #define CONFIG_SYS_CLK_FREQ 33333333
 #endif /* CONFIG_T_SH7706LSR */
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV 4
 #define CONFIG_SYS_HZ  1000