Merge tag 'u-boot-stm32-2019-10-23' of https://gitlab.denx.de/u-boot/custodians/u...

- Disable CONFIG_NET flag for MCU STM32
- Fix ramdisk_addr_r for stm32f746-disco
- Fix USB product id for stm32mp1

diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index bb169aaaf4b0b2c1bdf2a5a85a0761073345db67..df64f5415a588b06b2cc35aa2456393c79803ba7 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -68,12 +68,18 @@ static void __secure ls1_deepsleep_irq_cfg(void)
 
        ippdexpcr0 = in_be32(&rcpm->ippdexpcr0);
        /*
-        * Workaround: There is bug of register ippdexpcr1, when read it always
-        * returns zero, so its value is saved to a scrachpad register to be
-        * read, that is why we don't read it from register ippdexpcr1 itself.
+        * Workaround of errata A-008646
+        * Errata states that read to register ippdexpcr1 always returns
+        * zero irrespective of what value is written into it. So its value
+        * is first saved to a spare register and then read from it
         */
-       ippdexpcr1 = in_le32(&scfg->sparecr[7]);
-       out_be32(&rcpm->ippdexpcr1, ippdexpcr1);
+       ippdexpcr1 = in_be32(&scfg->sparecr[7]);
+
+       /*
+        * To allow OCRAM to be used as wakeup source in deep sleep,
+        * do not power it down.
+        */
+       out_be32(&rcpm->ippdexpcr1, ippdexpcr1 | RCPM_IPPDEXPCR1_OCRAM1);
 
        if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
                pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index a5d0b5370f8083f0230921e820f030777a87241a..8fd6c751c693852a7b6652b0904d73077f7d5882 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -59,6 +59,9 @@ static struct cpu_type cpu_type_list[] = {
        CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
        CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
        CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+       CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
+       CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
+       CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
        CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
        CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
        CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 19917b207aba33c7d083194e8b43cf7e4342f3f6..e9932095932b1d537c944c539537f1ae3e4cad46 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -401,6 +401,26 @@ void fdt_fixup_remove_jr(void *blob)
 }
 #endif
 
+#ifdef CONFIG_ARCH_LS1028A
+static void fdt_disable_multimedia(void *blob, unsigned int svr)
+{
+       int off;
+
+       if (IS_MULTIMEDIA_EN(svr))
+               return;
+
+       /* Disable eDP/LCD node */
+       off = fdt_node_offset_by_compatible(blob, -1, "arm,mali-dp500");
+       if (off != -FDT_ERR_NOTFOUND)
+               fdt_status_disabled(blob, off);
+
+       /* Disable GPU node */
+       off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu");
+       if (off != -FDT_ERR_NOTFOUND)
+               fdt_status_disabled(blob, off);
+}
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
        struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -462,4 +482,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
        fdt_fixup_msi(blob);
 #endif
+#ifdef CONFIG_ARCH_LS1028A
+       fdt_disable_multimedia(blob, svr);
+#endif
 }

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 3fd34e3a435d232ea2248219a75f02b467be6eda..1f1869e8cf6b5dc409306bc9da86d190e44e46c8 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -627,10 +627,19 @@ void fsl_lsch2_early_init_f(void)
 #endif
 #endif
        /* Make SEC reads and writes snoopable */
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+       setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
+                       SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+                       SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+                       SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+                       SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
+                       SCFG_SNPCNFGCR_SATAWRSNP);
+#else
        setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
                     SCFG_SNPCNFGCR_SECWRSNP |
                     SCFG_SNPCNFGCR_SATARDSNP |
                     SCFG_SNPCNFGCR_SATAWRSNP);
+#endif
 
        /*
         * Enable snoop requests and DVM message requests for

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 3a59abb10e5b75e448368818fc596933762048cb..862ec2e2f1f6880e843d55e574195a9a396dcc3a 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -409,6 +409,12 @@ struct ccsr_gur {
 #define SCFG_SNPCNFGCR_SECWRSNP                0x40000000
 #define SCFG_SNPCNFGCR_SATARDSNP       0x00800000
 #define SCFG_SNPCNFGCR_SATAWRSNP       0x00400000
+#define SCFG_SNPCNFGCR_USB1RDSNP       0x00200000
+#define SCFG_SNPCNFGCR_USB1WRSNP       0x00100000
+#define SCFG_SNPCNFGCR_USB2RDSNP       0x00008000
+#define SCFG_SNPCNFGCR_USB2WRSNP       0x00010000
+#define SCFG_SNPCNFGCR_USB3RDSNP       0x00002000
+#define SCFG_SNPCNFGCR_USB3WRSNP       0x00004000
 
 /* RGMIIPCR bit definitions*/
 #define SCFG_RGMIIPCR_EN_AUTO          BIT(3)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 234440b5fec1bd51650760540d9fa1436476ee03..35719d747b2f6cbbdc05aa43c2ca8b5e4cbcf5cd 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
  * Copyright 2015 Freescale Semiconductor
  */
 
@@ -83,6 +83,9 @@ enum boot_src get_boot_src(void);
 /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
 #define SVR_LS1043A_P23                0x879202
 #define SVR_LS1023A_P23                0x87920A
+#define SVR_LS1017A            0x870B24
+#define SVR_LS1018A            0x870B20
+#define SVR_LS1027A            0x870B04
 #define SVR_LS1028A            0x870B00
 #define SVR_LS1046A            0x870700
 #define SVR_LS1026A            0x870708
@@ -100,9 +103,9 @@ enum boot_src get_boot_src(void);
 #define SVR_LS2044A            0x870930
 #define SVR_LS2081A            0x870918
 #define SVR_LS2041A            0x870914
-#define SVR_LX2160A            0x873601
-#define SVR_LX2120A            0x873621
-#define SVR_LX2080A            0x873603
+#define SVR_LX2160A            0x873600
+#define SVR_LX2120A            0x873620
+#define SVR_LX2080A            0x873602
 
 #define SVR_MAJ(svr)           (((svr) >> 4) & 0xf)
 #define SVR_MIN(svr)           (((svr) >> 0) & 0xf)
@@ -112,6 +115,9 @@ enum boot_src get_boot_src(void);
 #ifdef CONFIG_ARCH_LX2160A
 #define IS_C_PROCESSOR(svr)    (!((svr >> 12) & 0x1))
 #endif
+#ifdef CONFIG_ARCH_LS1028A
+#define IS_MULTIMEDIA_EN(svr)  (!((svr >> 10) & 0x1))
+#endif
 #define IS_SVR_REV(svr, maj, min) \
                ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
 #define SVR_DEV(svr)           ((svr) >> 8)

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 137cd61804999a55e722bd6408cd649e64b9ed68..f2ba182346ef2429eac64155482d593320f2b87b 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -155,7 +155,7 @@ struct ccsr_gur {
 #define SCFG_ETSECCMCR_GE0_CLK125      0x00000000
 #define SCFG_ETSECCMCR_GE1_CLK125      0x08000000
 #define SCFG_PIXCLKCR_PXCKEN           0x80000000
-#define SCFG_QSPI_CLKSEL               0xc0100000
+#define SCFG_QSPI_CLKSEL               0x50100000
 #define SCFG_SNPCNFGCR_SEC_RD_WR       0xc0000000
 #define SCFG_SNPCNFGCR_DCU_RD_WR       0x03000000
 #define SCFG_SNPCNFGCR_SATA_RD_WR      0x00c00000

diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c
index 095971448fc48696b75694c60da620aef0e45134..a9606b88655a4bacd46b41d85d6033942dbadb38 100644 (file)
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -63,6 +63,10 @@ int board_init(void)
        gd->env_addr = (ulong)&default_environment[0];
 #endif
 
+#ifdef CONFIG_FSL_CAAM
+       sec_init();
+#endif
+
 #ifdef CONFIG_FSL_LS_PPA
        ppa_init();
 #endif

diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h
index 77aa22bfdee08bc960b5beab04623efb912efa7e..1b0f1566d3eb19f7ec34557d6bc455f55bcf6f56 100644 (file)
--- a/include/configs/ls1012afrwy.h
+++ b/include/configs/ls1012afrwy.h
@@ -23,6 +23,11 @@
 #define CONFIG_SYS_MEMTEST_START       0x80000000
 #define CONFIG_SYS_MEMTEST_END         0x9fffffff
 
+/* ENV */
+#define CONFIG_SYS_FSL_QSPI_BASE       0x40000000
+#define CONFIG_ENV_ADDR                        (CONFIG_SYS_FSL_QSPI_BASE + \
+                               CONFIG_ENV_OFFSET)
+
 #ifndef CONFIG_SPL_BUILD
 #undef BOOT_TARGET_DEVICES
 #define BOOT_TARGET_DEVICES(func) \

diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index f6640fa4994a180e55a71e5f23c3bb8451e2cfc7..a5e27404f86a7e28d6c4296a68965024487f3ae1 100644 (file)
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -17,6 +17,10 @@
 #define CONFIG_SYS_MEMTEST_END         0x9fffffff
 
 
+/* ENV */
+#define CONFIG_SYS_FSL_QSPI_BASE       0x40000000
+#define CONFIG_ENV_ADDR                        (CONFIG_SYS_FSL_QSPI_BASE + \
+                                        CONFIG_ENV_OFFSET)
 /*
  * I2C IO expander
  */