arm: Remove balloon3 board
authorSimon Glass <sjg@chromium.org>
Mon, 31 Aug 2015 01:18:55 +0000 (19:18 -0600)
committerTom Rini <trini@konsulko.com>
Fri, 11 Sep 2015 18:06:44 +0000 (14:06 -0400)
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
arch/arm/Kconfig
arch/arm/include/asm/mach-types.h
board/balloon3/Kconfig [deleted file]
board/balloon3/MAINTAINERS [deleted file]
board/balloon3/Makefile [deleted file]
board/balloon3/balloon3.c [deleted file]
configs/balloon3_defconfig [deleted file]
include/configs/balloon3.h [deleted file]

index 8085a24de2ecd97103499814501bbc042b0e7ac7..a501f15834714977ea9f0e6963c79c1c958efaf3 100644 (file)
@@ -662,10 +662,6 @@ config TARGET_LS1021ATWR
        select CPU_V7
        select SUPPORT_SPL
 
-config TARGET_BALLOON3
-       bool "Support balloon3"
-       select CPU_PXA
-
 config TARGET_H2200
        bool "Support h2200"
        select CPU_PXA
@@ -809,7 +805,6 @@ source "board/Marvell/gplugd/Kconfig"
 source "board/armadeus/apf27/Kconfig"
 source "board/armltd/vexpress/Kconfig"
 source "board/armltd/vexpress64/Kconfig"
-source "board/balloon3/Kconfig"
 source "board/bluegiga/apx4devkit/Kconfig"
 source "board/broadcom/bcm28155_ap/Kconfig"
 source "board/broadcom/bcmcygnus/Kconfig"
index e72184bd948950d649822e6109d6dd55994aca6d..b1caa16928cb9640aebe8df3d003ec086d83dfa6 100644 (file)
@@ -197,7 +197,6 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_SMDK2412             1009
 #define MACH_TYPE_SMDK2413             1022
 #define MACH_TYPE_AML_M5900            1024
-#define MACH_TYPE_BALLOON3             1029
 #define MACH_TYPE_ECBAT91              1072
 #define MACH_TYPE_ONEARM               1075
 #define MACH_TYPE_SMDK2443             1084
@@ -3332,18 +3331,6 @@ extern unsigned int __machine_arch_type;
 # define machine_is_aml_m5900()        (0)
 #endif
 
-#ifdef CONFIG_MACH_BALLOON3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type    __machine_arch_type
-# else
-#  define machine_arch_type    MACH_TYPE_BALLOON3
-# endif
-# define machine_is_balloon3() (machine_arch_type == MACH_TYPE_BALLOON3)
-#else
-# define machine_is_balloon3() (0)
-#endif
-
 #ifdef CONFIG_MACH_ECBAT91
 # ifdef machine_arch_type
 #  undef machine_arch_type
diff --git a/board/balloon3/Kconfig b/board/balloon3/Kconfig
deleted file mode 100644 (file)
index 53b7a9a..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BALLOON3
-
-config SYS_BOARD
-       default "balloon3"
-
-config SYS_CONFIG_NAME
-       default "balloon3"
-
-endif
diff --git a/board/balloon3/MAINTAINERS b/board/balloon3/MAINTAINERS
deleted file mode 100644 (file)
index df9a5bb..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-BALLOON3 BOARD
-M:     Marek Vasut <marek.vasut@gmail.com>
-S:     Maintained
-F:     board/balloon3/
-F:     include/configs/balloon3.h
-F:     configs/balloon3_defconfig
diff --git a/board/balloon3/Makefile b/board/balloon3/Makefile
deleted file mode 100644 (file)
index d7fb5e0..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Balloon3 Support
-#
-# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  := balloon3.o
diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c
deleted file mode 100644 (file)
index 458d90c..0000000
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * Balloon3 Support
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa.h>
-#include <serial.h>
-#include <asm/io.h>
-#include <spartan3.h>
-#include <command.h>
-#include <usb.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void balloon3_init_fpga(void);
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
-       /* We have RAM, disable cache */
-       dcache_disable();
-       icache_disable();
-
-       /* arch number of balloon3 */
-       gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
-
-       /* adress of boot parameters */
-       gd->bd->bi_boot_params = 0xa0000100;
-
-       /* Init the FPGA */
-       balloon3_init_fpga();
-
-       return 0;
-}
-
-int dram_init(void)
-{
-       pxa2xx_dram_init();
-       gd->ram_size = PHYS_SDRAM_1_SIZE;
-       return 0;
-}
-
-void dram_init_banksize(void)
-{
-       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-       gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-
-       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-       gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-       gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-}
-
-#ifdef CONFIG_CMD_USB
-int board_usb_init(int index, enum usb_init_type init)
-{
-       writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
-               ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
-               UHCHR);
-
-       writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
-
-       while (readl(UHCHR) & UHCHR_FSBIR)
-               ;
-
-       writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
-       writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
-
-       /* Clear any OTG Pin Hold */
-       if (readl(PSSR) & PSSR_OTGPH)
-               writel(readl(PSSR) | PSSR_OTGPH, PSSR);
-
-       writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
-       writel(readl(UHCRHDA) | 0x100, UHCRHDA);
-
-       /* Set port power control mask bits, only 3 ports. */
-       writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
-
-       /* enable port 2 */
-       writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
-               UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
-
-       return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-       return 0;
-}
-
-void usb_board_stop(void)
-{
-       writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
-       udelay(11);
-       writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
-
-       writel(readl(UHCCOMS) | 1, UHCCOMS);
-       udelay(10);
-
-       writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
-
-       return;
-}
-#endif
-
-#if defined(CONFIG_FPGA)
-/* Toggle GPIO103 and GPIO104 --  PROGB and RDnWR */
-int fpga_pgm_fn(int nassert, int nflush, int cookie)
-{
-       if (nassert)
-               writel(0x80, GPCR3);
-       else
-               writel(0x80, GPSR3);
-       if (nflush)
-               writel(0x100, GPCR3);
-       else
-               writel(0x100, GPSR3);
-       return nassert;
-}
-
-/* Check GPIO83 -- INITB */
-int fpga_init_fn(int cookie)
-{
-       return !(readl(GPLR2) & 0x80000);
-}
-
-/* Check GPIO84 -- BUSY */
-int fpga_busy_fn(int cookie)
-{
-       return !(readl(GPLR2) & 0x100000);
-}
-
-/* Check GPIO111 -- DONE */
-int fpga_done_fn(int cookie)
-{
-       return readl(GPLR3) & 0x8000;
-}
-
-/* Configure GPIO104 as GPIO and deassert it */
-int fpga_pre_config_fn(int cookie)
-{
-       writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
-       writel(0x100, GPCR3);
-       return 0;
-}
-
-/* Configure GPIO104 as nSKTSEL */
-int fpga_post_config_fn(int cookie)
-{
-       writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
-       return 0;
-}
-
-/* Toggle RDnWR */
-int fpga_wr_fn(int nassert_write, int flush, int cookie)
-{
-       udelay(1000);
-
-       if (nassert_write)
-               writel(0x100, GPCR3);
-       else
-               writel(0x100, GPSR3);
-
-       return nassert_write;
-}
-
-/* Write program to the FPGA */
-int fpga_wdata_fn(uchar data, int flush, int cookie)
-{
-       writeb(data, 0x10f00000);
-       return 0;
-}
-
-/* Toggle Clock pin -- NO-OP */
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
-       return assert_clk;
-}
-
-/* Toggle ChipSelect pin -- NO-OP */
-int fpga_cs_fn(int assert_clk, int flush, int cookie)
-{
-       return assert_clk;
-}
-
-xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = {
-       fpga_pre_config_fn,
-       fpga_pgm_fn,
-       fpga_init_fn,
-       NULL,   /* err */
-       fpga_done_fn,
-       fpga_clk_fn,
-       fpga_cs_fn,
-       fpga_wr_fn,
-       NULL,   /* rdata */
-       fpga_wdata_fn,
-       fpga_busy_fn,
-       NULL,   /* abort */
-       fpga_post_config_fn,
-};
-
-xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
-                       (void *)&balloon3_fpga_fns, 0);
-
-/* Initialize the FPGA */
-void balloon3_init_fpga(void)
-{
-       fpga_init();
-       fpga_add(fpga_xilinx, &fpga);
-}
-#else
-void balloon3_init_fpga(void) {}
-#endif /* CONFIG_FPGA */
diff --git a/configs/balloon3_defconfig b/configs/balloon3_defconfig
deleted file mode 100644 (file)
index bf524ce..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_BALLOON3=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h
deleted file mode 100644 (file)
index 124a766..0000000
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * Balloon3 configuration file
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef        __CONFIG_H
-#define        __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-#define        CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
-#define        CONFIG_BALLOON3                 1       /* Balloon3 board */
-
-/*
- * Environment settings
- */
-#define        CONFIG_ENV_OVERWRITE
-#define        CONFIG_SYS_MALLOC_LEN           (128*1024)
-#define        CONFIG_ARCH_CPU_INIT
-#define        CONFIG_BOOTCOMMAND                                              \
-       "fpga load 0x0 0x50000 0x62638; "                               \
-       "if usb reset && fatload usb 0 0xa4000000 uImage; then "        \
-               "bootm 0xa4000000; "                                    \
-       "fi; "                                                          \
-       "bootm 0xd0000;"
-#define        CONFIG_BOOTARGS                 "console=tty0 console=ttyS2,115200"
-#define        CONFIG_TIMESTAMP
-#define        CONFIG_BOOTDELAY                2       /* Autoboot delay */
-#define        CONFIG_CMDLINE_TAG
-#define        CONFIG_SETUP_MEMORY_TAGS
-#define        CONFIG_SYS_TEXT_BASE            0x0
-#define        CONFIG_LZMA                     /* LZMA compression support */
-
-/*
- * Serial Console Configuration
- */
-#define        CONFIG_PXA_SERIAL
-#define        CONFIG_STUART                   1
-#define CONFIG_CONS_INDEX              2
-#define        CONFIG_BAUDRATE                 115200
-
-/*
- * Bootloader Components Configuration
- */
-#undef CONFIG_CMD_ENV
-#define        CONFIG_CMD_USB
-#define        CONFIG_CMD_FPGA_LOADMK
-#undef CONFIG_LCD
-
-/*
- * KGDB
- */
-#ifdef CONFIG_CMD_KGDB
-#define        CONFIG_KGDB_BAUDRATE            230400  /* kgdb serial port speed */
-#endif
-
-/*
- * HUSH Shell Configuration
- */
-#define        CONFIG_SYS_HUSH_PARSER          1
-
-#define        CONFIG_SYS_LONGHELP
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define        CONFIG_SYS_PROMPT               "$ "
-#else
-#endif
-#define        CONFIG_SYS_CBSIZE               256
-#define        CONFIG_SYS_PBSIZE               \
-       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define        CONFIG_SYS_MAXARGS              16
-#define        CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
-#define        CONFIG_SYS_DEVICE_NULLDEV       1
-
-/*
- * Clock Configuration
- */
-#define        CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
-
-/*
- * DRAM Map
- */
-#define        CONFIG_NR_DRAM_BANKS            3               /* 3 banks of DRAM */
-#define        PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
-#define        PHYS_SDRAM_1_SIZE               0x08000000      /* 128 MB */
-#define        PHYS_SDRAM_2                    0xb0000000      /* SDRAM Bank #2 */
-#define        PHYS_SDRAM_2_SIZE               0x08000000      /* 128 MB */
-#define        PHYS_SDRAM_3                    0x80000000      /* SDRAM Bank #3 */
-#define        PHYS_SDRAM_3_SIZE               0x08000000      /* 128 MB */
-
-#define        CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
-#define        CONFIG_SYS_DRAM_SIZE            0x18000000      /* 384 MB DRAM */
-
-#define        CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
-#define        CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
-
-#define        CONFIG_SYS_LOAD_ADDR            0xa1000000
-
-#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
-#define        CONFIG_SYS_INIT_SP_ADDR         \
-       (PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
-
-/*
- * NOR FLASH
- */
-#ifdef CONFIG_CMD_FLASH
-#define        PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
-#define        PHYS_FLASH_SIZE                 0x00800000      /* 8 MB */
-#define        CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
-
-#define        CONFIG_SYS_FLASH_CFI
-#define        CONFIG_FLASH_CFI_DRIVER         1
-#define        CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
-
-#define        CONFIG_SYS_MAX_FLASH_BANKS      1
-#define        CONFIG_SYS_MAX_FLASH_SECT       256
-
-#define        CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
-
-#define        CONFIG_SYS_FLASH_ERASE_TOUT     240000
-#define        CONFIG_SYS_FLASH_WRITE_TOUT     240000
-#define        CONFIG_SYS_FLASH_LOCK_TOUT      240000
-#define        CONFIG_SYS_FLASH_UNLOCK_TOUT    240000
-#define        CONFIG_SYS_FLASH_PROTECTION
-#define        CONFIG_ENV_IS_IN_FLASH
-#else
-#define        CONFIG_SYS_NO_FLASH
-#define        CONFIG_ENV_IS_NOWHERE
-#endif
-
-#define        CONFIG_SYS_MONITOR_BASE         0x000000
-#define        CONFIG_SYS_MONITOR_LEN          0x40000
-
-#define        CONFIG_ENV_SIZE                 0x2000
-#define        CONFIG_ENV_ADDR                 0x40000
-#define        CONFIG_ENV_SECT_SIZE            0x10000
-
-/*
- * GPIO settings
- */
-#define        CONFIG_SYS_GPSR0_VAL    0x307dc7fd
-#define        CONFIG_SYS_GPSR1_VAL    0x03cffa4e
-#define        CONFIG_SYS_GPSR2_VAL    0x7131c000
-#define        CONFIG_SYS_GPSR3_VAL    0x01e1f3ff
-
-#define        CONFIG_SYS_GPCR0_VAL    0x0
-#define        CONFIG_SYS_GPCR1_VAL    0x0
-#define        CONFIG_SYS_GPCR2_VAL    0x0
-#define        CONFIG_SYS_GPCR3_VAL    0x0
-
-#define        CONFIG_SYS_GPDR0_VAL    0xc0f98e02
-#define        CONFIG_SYS_GPDR1_VAL    0xfcffa8b7
-#define        CONFIG_SYS_GPDR2_VAL    0x22e3ffff
-#define        CONFIG_SYS_GPDR3_VAL    0x000201fe
-
-#define        CONFIG_SYS_GAFR0_L_VAL  0x96c00000
-#define        CONFIG_SYS_GAFR0_U_VAL  0xa5e5459b
-#define        CONFIG_SYS_GAFR1_L_VAL  0x699b759a
-#define        CONFIG_SYS_GAFR1_U_VAL  0xaaa5a5aa
-#define        CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
-#define        CONFIG_SYS_GAFR2_U_VAL  0x01f9a6aa
-#define        CONFIG_SYS_GAFR3_L_VAL  0x54510003
-#define        CONFIG_SYS_GAFR3_U_VAL  0x00001599
-
-#define        CONFIG_SYS_PSSR_VAL     0x30
-
-/*
- * Clock settings
- */
-#define        CONFIG_SYS_CKEN         0xffffffff
-#define        CONFIG_SYS_CCCR         0x00000290
-
-/*
- * Memory settings
- */
-#define        CONFIG_SYS_MSC0_VAL     0x7ff07ff8
-#define        CONFIG_SYS_MSC1_VAL     0x7ff07ff0
-#define        CONFIG_SYS_MSC2_VAL     0x74a42491
-#define        CONFIG_SYS_MDCNFG_VAL   0x89d309d3
-#define        CONFIG_SYS_MDREFR_VAL   0x001d8018
-#define        CONFIG_SYS_MDMRS_VAL    0x00220022
-#define        CONFIG_SYS_FLYCNFG_VAL  0x00000000
-#define        CONFIG_SYS_SXCNFG_VAL   0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define        CONFIG_SYS_MECR_VAL     0x00000000
-#define        CONFIG_SYS_MCMEM0_VAL   0x00014307
-#define        CONFIG_SYS_MCMEM1_VAL   0x00014307
-#define        CONFIG_SYS_MCATT0_VAL   0x0001c787
-#define        CONFIG_SYS_MCATT1_VAL   0x0001c787
-#define        CONFIG_SYS_MCIO0_VAL    0x0001430f
-#define        CONFIG_SYS_MCIO1_VAL    0x0001430f
-
-/*
- * LCD
- */
-#ifdef CONFIG_LCD
-#define        CONFIG_BALLOON3LCD
-#define        CONFIG_VIDEO_LOGO
-#define        CONFIG_CMD_BMP
-#define        CONFIG_SPLASH_SCREEN
-#define        CONFIG_SPLASH_SCREEN_ALIGN
-#define        CONFIG_VIDEO_BMP_GZIP
-#define        CONFIG_VIDEO_BMP_RLE8
-#define        CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)
-#endif
-
-/*
- * USB
- */
-#ifdef CONFIG_CMD_USB
-#define        CONFIG_USB_OHCI_NEW
-#define        CONFIG_SYS_USB_OHCI_CPU_INIT
-#define        CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define        CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
-#define        CONFIG_SYS_USB_OHCI_REGS_BASE   0x4C000000
-#define        CONFIG_SYS_USB_OHCI_SLOT_NAME   "balloon3"
-#define        CONFIG_USB_STORAGE
-#define        CONFIG_DOS_PARTITION
-#define        CONFIG_CMD_FAT
-#define        CONFIG_CMD_EXT2
-#endif
-
-/*
- * FPGA
- */
-#ifdef CONFIG_CMD_FPGA
-#define        CONFIG_FPGA
-#define        CONFIG_FPGA_XILINX
-#define        CONFIG_FPGA_SPARTAN3
-#define        CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define        CONFIG_SYS_FPGA_WAIT    1000
-#define        CONFIG_MAX_FPGA_DEVICES 1
-#endif
-
-#endif /* __CONFIG_H */