block: Add support for Ceva sata

Initial Ceva Sata init code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 0f44b04c1efa85231e7640450cc6cae9955468dd..087578cb6b9c0cf823378f27b415b2b8fe54c2af 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -7,6 +7,7 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <sata.h>
 #include <ahci.h>
 #include <scsi.h>
 #include <asm/arch/clk.h>
@@ -185,6 +186,9 @@ void reset_cpu(ulong addr)
 #ifdef CONFIG_SCSI_AHCI_PLAT
 void scsi_init(void)
 {
+#if defined(CONFIG_SATA_CEVA)
+       init_sata(0);
+#endif
        ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
        scsi_scan(1);
 }

diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index b4cbb0934413822ccfbc0c3a2594ae2f2cc91ee3..a43492f208207c915692a87206ea97b4ce8c24e8 100644 (file)
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_LIBATA) += libata.o
 obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
 obj-$(CONFIG_MX51_PATA) += mxc_ata.o
 obj-$(CONFIG_PATA_BFIN) += pata_bfin.o
+obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
 obj-$(CONFIG_SATA_DWC) += sata_dwc.o
 obj-$(CONFIG_SATA_MV) += sata_mv.o
 obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o

diff --git a/drivers/block/sata_ceva.c b/drivers/block/sata_ceva.c
new file mode 100644 (file)
index 0000000..dcc3b90
--- /dev/null
+++ b/drivers/block/sata_ceva.c
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2015 - 2016 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#include <common.h>
+#include <netdev.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <asm/arch/hardware.h>
+
+#include <asm/io.h>
+
+/* Vendor Specific Register Offsets */
+#define AHCI_VEND_PCFG  0xA4
+#define AHCI_VEND_PPCFG 0xA8
+#define AHCI_VEND_PP2C  0xAC
+#define AHCI_VEND_PP3C  0xB0
+#define AHCI_VEND_PP4C  0xB4
+#define AHCI_VEND_PP5C  0xB8
+#define AHCI_VEND_PAXIC 0xC0
+#define AHCI_VEND_PTC   0xC8
+
+/* Vendor Specific Register bit definitions */
+#define PAXIC_ADBW_BW64 0x1
+#define PAXIC_MAWIDD   (1 << 8)
+#define PAXIC_MARIDD   (1 << 16)
+#define PAXIC_OTL      (0x4 << 20)
+
+#define PCFG_TPSS_VAL  (0x32 << 16)
+#define PCFG_TPRS_VAL  (0x2 << 12)
+#define PCFG_PAD_VAL   0x2
+
+#define PPCFG_TTA      0x1FFFE
+#define PPCFG_PSSO_EN  (1 << 28)
+#define PPCFG_PSS_EN   (1 << 29)
+#define PPCFG_ESDF_EN  (1 << 31)
+
+#define PP2C_CIBGMN    0x0F
+#define PP2C_CIBGMX    (0x25 << 8)
+#define PP2C_CIBGN     (0x18 << 16)
+#define PP2C_CINMP     (0x29 << 24)
+
+#define PP3C_CWBGMN    0x04
+#define PP3C_CWBGMX    (0x0B << 8)
+#define PP3C_CWBGN     (0x08 << 16)
+#define PP3C_CWNMP     (0x0F << 24)
+
+#define PP4C_BMX       0x0a
+#define PP4C_BNM       (0x08 << 8)
+#define PP4C_SFD       (0x4a << 16)
+#define PP4C_PTST      (0x06 << 24)
+
+#define PP5C_RIT       0x60216
+#define PP5C_RCT       (0x7f0 << 20)
+
+#define PTC_RX_WM_VAL  0x40
+#define PTC_RSVD       (1 << 27)
+
+#define PORT0_BASE     0x100
+#define PORT1_BASE     0x180
+
+/* Port Control Register Bit Definitions */
+#define PORT_SCTL_SPD_GEN3     (0x3 << 4)
+#define PORT_SCTL_SPD_GEN2     (0x2 << 4)
+#define PORT_SCTL_SPD_GEN1     (0x1 << 4)
+#define PORT_SCTL_IPM          (0x3 << 8)
+
+#define PORT_BASE      0x100
+#define PORT_OFFSET    0x80
+#define NR_PORTS       2
+#define DRV_NAME       "ahci-ceva"
+#define CEVA_FLAG_BROKEN_GEN2  1
+
+int init_sata(int dev)
+{
+       ulong tmp;
+       ulong mmio = ZYNQMP_SATA_BASEADDR;
+       int i;
+
+       /*
+        * AXI Data bus width to 64
+        * Set Mem Addr Read, Write ID for data transfers
+        * Transfer limit to 72 DWord
+        */
+       tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
+       writel(tmp, mmio + AHCI_VEND_PAXIC);
+
+       /* Set AHCI Enable */
+       tmp = readl(mmio + HOST_CTL);
+       tmp |= HOST_AHCI_EN;
+       writel(tmp, mmio + HOST_CTL);
+
+       for (i = 0; i < NR_PORTS; i++) {
+               /* TPSS TPRS scalars, CISE and Port Addr */
+               tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
+               writel(tmp, mmio + AHCI_VEND_PCFG);
+
+               /* Port Phy Cfg register enables */
+               tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
+               writel(tmp, mmio + AHCI_VEND_PPCFG);
+
+               /* Rx Watermark setting  */
+               tmp = PTC_RX_WM_VAL | PTC_RSVD;
+               writel(tmp, mmio + AHCI_VEND_PTC);
+
+               /* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
+               tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
+               writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
+       }
+       return 0;
+}

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 4062e01824e3ef19335b32f75042c9c7b6d14f8f..8c760967f6d619779197deeedb8cd811361b926f 100644 (file)
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -226,7 +226,7 @@
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID    1
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID    2
 #define CONFIG_SYS_SCSI_MAX_LUN                1
 #define CONFIG_SYS_SCSI_MAX_DEVICE     (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
                                         CONFIG_SYS_SCSI_MAX_LUN)