85xx: Limit CPU2 workaround to parts that have the errata

Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index dc39fbe8dc5bad56219de7e35f909b247b52a383..efe2a3a3def57c761ff648e6a5a7b71998475b6e 100644 (file)
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -59,6 +59,7 @@ int checkboard (void)
        uint pci_slot = get_pci_slot ();
 
        uint cpu_board_rev = get_cpu_board_revision ();
+       uint svr;
 
        printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
                get_board_version (), pci_slot);
@@ -71,12 +72,16 @@ int checkboard (void)
         */
        local_bus_init ();
 
+       svr = get_svr();
+
        /*
         * Fix CPU2 errata: A core hang possible while executing a
         * msync instruction and a snoopable transaction from an I/O
         * master tagged to make quick forward progress is present.
+        * Fixed in Silicon Rev.2.1
         */
-       ecm->eebpcr |= (1 << 16);
+       if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
+               ecm->eebpcr |= (1 << 16);
 
        /*
         * Hack TSEC 3 and 4 IO voltages.