rockchip: config: rk3399: enable SPL config for evb-rk3399
authorKever Yang <kever.yang@rock-chips.com>
Wed, 22 Feb 2017 08:56:38 +0000 (16:56 +0800)
committerSimon Glass <sjg@chromium.org>
Thu, 16 Mar 2017 22:03:46 +0000 (16:03 -0600)
Enable all the CONFIGs which need by SPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Drop CONFIG_ROCKCHIP_DWMMC for now due to build error:
Move changes to arch/arm/mach-rockchip/Kconfig to this patch:
Signed-off-by: Simon Glass <sjg@chromium.org>
arch/arm/mach-rockchip/Kconfig
configs/evb-rk3399_defconfig
include/configs/rk3399_common.h

index ba9fbbbd33a7d3a9c81d388ef628701c42d444b2..565908af346f8226ca1e9250762022e9a8a7917d 100644 (file)
@@ -41,6 +41,9 @@ config ROCKCHIP_RK3288
 config ROCKCHIP_RK3399
        bool "Support Rockchip RK3399"
        select ARM64
+       select SUPPORT_SPL
+       select SPL
+       select SPL_SEPARATE_BSS
        help
          The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
          and quad-core Cortex-A53.
index ad51ed21dd57557fe84fc33b571b9b3504dddc33..7ef7cb021e616c817f79256b7dd21a76f1a6710c 100644 (file)
@@ -3,7 +3,16 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb"
 CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_ATF_SUPPORT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
+CONFIG_SPL_ATF_TEXT_BASE=0x00010000
 # CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPT=y
@@ -12,20 +21,28 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
+CONFIG_CMD_PXE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_OF_PLATDATA=y
 CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
 CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
 CONFIG_ROCKCHIP_RK3399_PINCTRL=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
+CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
index 6921f68068e3400d1836f81255fbc6bdb9aff685..eb383764fe3bbb16d2fce60b02b364d0bd523b20 100644 (file)
 #define CONFIG_SYS_MALLOC_LEN          (32 << 20)
 #define CONFIG_SYS_CBSIZE              1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
 
 #define CONFIG_SYS_NS16550_MEM32