x86: Kconfig: Divide the target selection to vendor/model

Let arch/x86/Kconfig prompt board vendor first, then select
the board model under that vendor. This way arch/x86/Kconfig
only needs concern board vendor and leave the supported target
list to board/<vendor>/Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index aaceaef8b5e9f438370d32718c8e22f982167e47..c3cc144d9ced3bb1c213c13846ea6c6455261f6b 100644 (file)
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -11,79 +11,25 @@ config SYS_VSNPRINTF
        default y
 
 choice
-       prompt "Target select"
+       prompt "Mainboard vendor"
+       default VENDOR_COREBOOT
 
-config TARGET_COREBOOT
-       bool "Support coreboot"
-       help
-         This target is used for running U-Boot on top of Coreboot. In
-         this case Coreboot does the early inititalisation, and U-Boot
-         takes over once the RAM, video and CPU are fully running.
-         U-Boot is loaded as a fallback payload from Coreboot, in
-         Coreboot terminology. This method was used for the Chromebook
-         Pixel when launched.
-
-config TARGET_CHROMEBOOK_LINK
-       bool "Support Chromebook link"
-       help
-         This is the Chromebook Pixel released in 2013. It uses an Intel
-         i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
-         SDRAM. It has a Panther Point platform controller hub, PCIe
-         WiFi and Bluetooth. It also includes a 720p webcam, USB SD
-         reader, microphone and speakers, display port and 32GB SATA
-         solid state drive. There is a Chrome OS EC connected on LPC,
-         and it provides a 2560x1700 high resolution touch-enabled LCD
-         display.
-
-config TARGET_CHROMEBOX_PANTHER
-       bool "Support Chromebox panther (not available)"
-       select n
-       help
-         Note: At present this must be used with Coreboot. See README.x86
-         for instructions.
-
-         This is the Asus Chromebox CN60 released in 2014. It uses an Intel
-         Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a
-         Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also
-         includes a USB SD reader, four USB3 ports, display port and HDMI
-         video output and a 16GB SATA solid state drive. There is no Chrome
-         OS EC on this model.
-
-config TARGET_CROWNBAY
-       bool "Support Intel Crown Bay CRB"
-       help
-         This is the Intel Crown Bay Customer Reference Board. It contains
-         the Intel Atom Processor E6xx populated on the COM Express module
-         with 1GB DDR2 soldered down memory and a carrier board with the
-         Intel Platform Controller Hub EG20T, other system components and
-         peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
-
-config TARGET_MINNOWMAX
-       bool "Support Intel Minnowboard MAX"
-       help
-         This is the Intel Minnowboard MAX. It contains an Atom E3800
-         processor in a small form factor with Ethernet, micro-SD, USB 2,
-         USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
-         It requires some binary blobs - see README.x86 for details.
+config VENDOR_COREBOOT
+       bool "coreboot"
 
-         Note that PCIE_ECAM_BASE is set up by the FSP so the value used
-         by U-Boot matches that value.
+config VENDOR_GOOGLE
+       bool "Google"
 
-config TARGET_GALILEO
-       bool "Support Intel Galileo"
-       help
-         This is the Intel Galileo board, which is the first in a family of
-         Arduino-certified development and prototyping boards based on Intel
-         architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
-         single-core, single-thread, Intel Pentium processor instrunction set
-         architecture (ISA) compatible, operating at speeds up to 400Mhz,
-         along with 256MB DDR3 memory. It supports a wide range of industry
-         standard I/O interfaces, including a full-sized mini-PCIe slot,
-         one 100Mb Ethernet port, a microSD card slot, a USB host port and
-         a USB client port.
+config VENDOR_INTEL
+       bool "Intel"
 
 endchoice
 
+# board-specific options below
+source "board/coreboot/Kconfig"
+source "board/google/Kconfig"
+source "board/intel/Kconfig"
+
 config DM_SPI
        default y
 
@@ -473,18 +419,6 @@ config IRQ_SLOT_COUNT
          should be enough for most boards. If this does not fit your board,
          change it according to your needs.
 
-source "board/coreboot/coreboot/Kconfig"
-
-source "board/google/chromebook_link/Kconfig"
-
-source "board/google/chromebox_panther/Kconfig"
-
-source "board/intel/crownbay/Kconfig"
-
-source "board/intel/minnowmax/Kconfig"
-
-source "board/intel/galileo/Kconfig"
-
 config PCIE_ECAM_BASE
        hex
        default 0xe0000000

diff --git a/board/coreboot/Kconfig b/board/coreboot/Kconfig
new file mode 100644 (file)
index 0000000..dc9b70f
--- /dev/null
+++ b/board/coreboot/Kconfig
@@ -0,0 +1,26 @@
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+if VENDOR_COREBOOT
+
+choice
+       prompt "Mainboard model"
+
+config TARGET_COREBOOT
+       bool "coreboot"
+       help
+         This target is used for running U-Boot on top of coreboot. In
+         this case coreboot does the early inititalisation, and U-Boot
+         takes over once the RAM, video and CPU are fully running.
+         U-Boot is loaded as a fallback payload from coreboot, in
+         coreboot terminology. This method was used for the Chromebook
+         Pixel when launched.
+
+endchoice
+
+source "board/coreboot/coreboot/Kconfig"
+
+endif

diff --git a/board/google/Kconfig b/board/google/Kconfig
new file mode 100644 (file)
index 0000000..302f68e
--- /dev/null
+++ b/board/google/Kconfig
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+if VENDOR_GOOGLE
+
+choice
+       prompt "Mainboard model"
+
+config TARGET_CHROMEBOOK_LINK
+       bool "Chromebook link"
+       help
+         This is the Chromebook Pixel released in 2013. It uses an Intel
+         i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
+         SDRAM. It has a Panther Point platform controller hub, PCIe
+         WiFi and Bluetooth. It also includes a 720p webcam, USB SD
+         reader, microphone and speakers, display port and 32GB SATA
+         solid state drive. There is a Chrome OS EC connected on LPC,
+         and it provides a 2560x1700 high resolution touch-enabled LCD
+         display.
+
+config TARGET_CHROMEBOX_PANTHER
+       bool "Chromebox panther (not available)"
+       select n
+       help
+         Note: At present this must be used with coreboot. See README.x86
+         for instructions.
+
+         This is the Asus Chromebox CN60 released in 2014. It uses an Intel
+         Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a
+         Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also
+         includes a USB SD reader, four USB3 ports, display port and HDMI
+         video output and a 16GB SATA solid state drive. There is no Chrome
+         OS EC on this model.
+
+endchoice
+
+source "board/google/chromebook_link/Kconfig"
+source "board/google/chromebox_panther/Kconfig"
+
+endif

diff --git a/board/intel/Kconfig b/board/intel/Kconfig
new file mode 100644 (file)
index 0000000..7fe21b9
--- /dev/null
+++ b/board/intel/Kconfig
@@ -0,0 +1,51 @@
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+if VENDOR_INTEL
+
+choice
+       prompt "Mainboard model"
+
+config TARGET_CROWNBAY
+       bool "Crown Bay"
+       help
+         This is the Intel Crown Bay Customer Reference Board. It contains
+         the Intel Atom Processor E6xx populated on the COM Express module
+         with 1GB DDR2 soldered down memory and a carrier board with the
+         Intel Platform Controller Hub EG20T, other system components and
+         peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
+
+config TARGET_GALILEO
+       bool "Galileo"
+       help
+         This is the Intel Galileo board, which is the first in a family of
+         Arduino-certified development and prototyping boards based on Intel
+         architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
+         single-core, single-thread, Intel Pentium processor instrunction set
+         architecture (ISA) compatible, operating at speeds up to 400Mhz,
+         along with 256MB DDR3 memory. It supports a wide range of industry
+         standard I/O interfaces, including a full-sized mini-PCIe slot,
+         one 100Mb Ethernet port, a microSD card slot, a USB host port and
+         a USB client port.
+
+config TARGET_MINNOWMAX
+       bool "Minnowboard MAX"
+       help
+         This is the Intel Minnowboard MAX. It contains an Atom E3800
+         processor in a small form factor with Ethernet, micro-SD, USB 2,
+         USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
+         It requires some binary blobs - see README.x86 for details.
+
+         Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+         by U-Boot matches that value.
+
+endchoice
+
+source "board/intel/crownbay/Kconfig"
+source "board/intel/galileo/Kconfig"
+source "board/intel/minnowmax/Kconfig"
+
+endif

diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index fe2610a351e5eb4c8d8d4133d0aa7afbce263b56..9cfc65b5b7d87014ad3797935addbc3a35f6bbf4 100644 (file)
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
 CONFIG_X86=y
+CONFIG_VENDOR_GOOGLE=y
 CONFIG_TARGET_CHROMEBOOK_LINK=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_SEPARATE=y

diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index 0613cd64a993dd0158d007bd1a355a2ebfb8726a..c4db232d2d908cc8b178df0d0bef1318cb729558 100644 (file)
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
 CONFIG_X86=y
+CONFIG_VENDOR_GOOGLE=y
 CONFIG_TARGET_CHROMEBOX_PANTHER=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_SEPARATE=y

diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index 0249172feb309feb15400bd5daf9c77db16855cb..eb192ae42c4051e2533fe708d09b6186ccc1655a 100644 (file)
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x01110000"
 CONFIG_X86=y
+CONFIG_VENDOR_COREBOOT=y
 CONFIG_TARGET_COREBOOT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM_PCI=y

diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 47763f9597679d054ed16d20a288d7109289f8f7..de84650609942b12037ccc37cbda331e8931e58b 100644 (file)
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
 CONFIG_X86=y
+CONFIG_VENDOR_INTEL=y
 CONFIG_TARGET_CROWNBAY=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_SEPARATE=y

diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 9b0f969c53db684063872e90e3243d0072488fe4..787e15f568084a05926e55f8ec28c2f0386a283a 100644 (file)
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff10000"
 CONFIG_X86=y
+CONFIG_VENDOR_INTEL=y
 CONFIG_TARGET_GALILEO=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_SEPARATE=y

diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index d1add190eb9d16b12414bb57ae3aea90da0c8d6f..c4dbfcacc591967a76bfcfe41538aaef8d6986f0 100644 (file)
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
 CONFIG_X86=y
+CONFIG_VENDOR_INTEL=y
 CONFIG_TARGET_MINNOWMAX=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_SEPARATE=y