u32 ret_payload[PAYLOAD_ARG_CNT];
u32 div;
- versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
+ xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
div = ret_payload[1];
return div;
{
u32 ret_payload[PAYLOAD_ARG_CNT];
- versal_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
+ xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
return div;
}
u32 ret_payload[PAYLOAD_ARG_CNT];
int ref;
- versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
+ xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
ref = ret_payload[0];
if (!(ref & 1))
return ref_clk;
u32 parent_rate, parent_id;
u32 id = clk_id & 0xFFF;
- versal_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
+ xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
res = ret_payload[1];
if (!res) {
printf("0%x PLL not enabled\n", clk_id);
parent_id = clock[clock[id].parent[0].id].clk_id;
parent_rate = versal_clock_ref(parent_id);
- versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
+ xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
fbdiv = ret_payload[1];
- versal_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
+ xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
frac = ret_payload[1];
freq = (fbdiv * parent_rate) >> (1 << frac);
u32 id = clk_id & 0xFFF;
if (versal_clock_mux(clk_id)) {
- versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
+ xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
ret_payload);
parent_id = ret_payload[1];
}
void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
u32 *ret_payload);
-int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
+int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
u32 arg3, u32 *ret_payload);
#endif /* _ZYNQMP_FIRMWARE_H_ */