static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
+/******************************************
+ * get_cpu_type(void) - extract cpu info
+ ******************************************/
+u32 get_cpu_type(void)
+{
+ return readl(&ctrl_base->ctrl_omap_stat);
+}
+
/******************************************
* get_cpu_rev(void) - extract version info
******************************************/
*********************************************************************/
void display_board_info(u32 btype)
{
- char *mem_s, *sec_s;
+ char *cpu_s, *mem_s, *sec_s;
+
+ switch (get_cpu_type()) {
+ case OMAP3503:
+ cpu_s = "3503";
+ break;
+ case OMAP3515:
+ cpu_s = "3515";
+ break;
+ case OMAP3525:
+ cpu_s = "3525";
+ break;
+ case OMAP3530:
+ cpu_s = "3530";
+ break;
+ default:
+ cpu_s = "35XX";
+ break;
+ }
if (is_mem_sdr())
mem_s = "mSDR";
sec_s = "?";
}
- printf("OMAP%s-%s rev %d, CPU-OPP2 L3-165MHz\n", sysinfo.cpu_string,
+
+ printf("OMAP%s-%s rev %d, CPU-OPP2 L3-165MHz\n", cpu_s,
sec_s, get_cpu_rev());
printf("%s + %s/%s\n", sysinfo.board_string,
mem_s, sysinfo.nand_string);
unsigned short gpmc_nwe; /* 0xC4 */
unsigned char res2[0x22A];
unsigned int status; /* 0x2F0 */
+ unsigned int gpstatus; /* 0x2F4 */
+ unsigned char res3[0x08];
+ unsigned int rpubkey_0; /* 0x300 */
+ unsigned int rpubkey_1; /* 0x304 */
+ unsigned int rpubkey_2; /* 0x308 */
+ unsigned int rpubkey_3; /* 0x30C */
+ unsigned int rpubkey_4; /* 0x310 */
+ unsigned char res4[0x04];
+ unsigned int randkey_0; /* 0x318 */
+ unsigned int randkey_1; /* 0x31C */
+ unsigned int randkey_2; /* 0x320 */
+ unsigned int randkey_3; /* 0x324 */
+ unsigned char res5[0x124];
+ unsigned int ctrl_omap_stat; /* 0x44C */
} ctrl_t;
#else /* __ASSEMBLY__ */
#define CONTROL_STATUS 0x2F0
#endif /* __ASSEMBLY__ */
+/* cpu type */
+#define OMAP3503 0x5c00
+#define OMAP3515 0x1c00
+#define OMAP3525 0x4c00
+#define OMAP3530 0x0c00
+
/* device type */
#define DEVICE_MASK (0x7 << 8)
#define SYSBOOT_MASK 0x1F