rockchip: rk3036: sync os_reg2 define with other soc

Rockchip using the same bit definition for dram info and write
to os_reg, the col and bw info is not correct and let's fix it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index ec8305cff82c5048f8456fb52c8a351e490e7ce4..460dd6074e607c00e5c565ec7c8ae697d1d97f71 100644 (file)
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -710,11 +710,12 @@ static void sdram_all_config(struct rk3036_sdram_priv *priv)
        os_reg = config.ddr_type << DDR_TYPE_SHIFT |
                        0 << DDR_CHN_CNT_SHIFT |
                        (config.rank - 1) << DDR_RANK_CNT_SHIFT |
-                       (config.col - 1) << DDR_COL_SHIFT |
+                       (config.col - 9) << DDR_COL_SHIFT |
                        (config.bank == 3 ? 0 : 1) << DDR_BANK_SHIFT |
                        (config.cs0_row - 13) << DDR_CS0_ROW_SHIFT |
                        cs1_row << DDR_CS1_ROW_SHIFT |
-                       1 << DDR_BW_SHIFT | config.bw << DDR_DIE_BW_SHIFT;
+                       1 << DDR_BW_SHIFT |
+                       (2 >> config.bw) << DDR_DIE_BW_SHIFT;
        writel(os_reg, &priv->grf->os_reg[1]);
 }