phy: marvell: a3700: Use reg_set16 instead of phy_write16

The macro phy_write16 is not used by the rest of the code,
phy_read16 is not used at all.
We also change the macro SGMIIPHY_ADDR to a static inline function.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
index 71fd8dcbdf67d45195b00dac8d1aebe7370fcf09..3d913f434287ca1d0cbb06b3da1bd02a9241e459 100644 (file)
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -610,7 +610,7 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed)
                        val = sgmii_phy_init[addr];
                }
 
-               phy_write16(lane, addr, val, 0xFFFF);
+               reg_set16(sgmiiphy_addr(lane, addr), val, 0xFFFF);
        }
 }
 
@@ -673,26 +673,26 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
        mdelay(10);
 
        /* 9. Program COMPHY register PHY_MODE */
-       phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR,
-                   PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask);
+       reg_set16(sgmiiphy_addr(lane, PHY_PWR_PLL_CTRL_ADDR),
+                 PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask);
 
        /*
         * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK
         *     source
         */
-       phy_write16(lane, PHY_MISC_REG0_ADDR, 0, rb_ref_clk_sel);
+       reg_set16(sgmiiphy_addr(lane, PHY_MISC_REG0_ADDR), 0, rb_ref_clk_sel);
 
        /*
         * 11. Set correct reference clock frequency in COMPHY register
         *     REF_FREF_SEL.
         */
        if (get_ref_clk() == 40) {
-               phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR,
-                           0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
+               reg_set16(sgmiiphy_addr(lane, PHY_PWR_PLL_CTRL_ADDR),
+                         0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
        } else {
                /* 25MHz */
-               phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR,
-                           0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
+               reg_set16(sgmiiphy_addr(lane, PHY_PWR_PLL_CTRL_ADDR),
+                         0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
        }
 
        /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */
@@ -708,7 +708,8 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
         *     bus width
         */
        /* 10bit */
-       phy_write16(lane, PHY_DIG_LB_EN_ADDR, 0, rf_data_width_mask);
+       reg_set16(sgmiiphy_addr(lane, PHY_DIG_LB_EN_ADDR), 0,
+                 rf_data_width_mask);
 
        /*
         * 14. As long as DFE function needs to be enabled in any mode,
@@ -751,10 +752,12 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
         * 18. Check the PHY Polarity invert bit
         */
        if (invert & PHY_POLARITY_TXD_INVERT)
-               phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_txd_inv, 0);
+               reg_set16(sgmiiphy_addr(lane, PHY_SYNC_PATTERN_ADDR),
+                         phy_txd_inv, 0);
 
        if (invert & PHY_POLARITY_RXD_INVERT)
-               phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_rxd_inv, 0);
+               reg_set16(sgmiiphy_addr(lane, PHY_SYNC_PATTERN_ADDR),
+                         phy_rxd_inv, 0);
 
        /*
         * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1

diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h
index d41a1aa5162d91f34639884c7eb01064318d43c4..ca8c648c35281f97beeb4b37687b11ed59861774 100644 (file)
--- a/drivers/phy/marvell/comphy_a3700.h
+++ b/drivers/phy/marvell/comphy_a3700.h
@@ -60,13 +60,14 @@
 #define USB32_CTRL_BASE                        MVEBU_REG(0x05D800)
 #define USB3PHY_SHFT                   2
 
-#define SGMIIPHY_BASE(l)       (l == 1 ? USB3PHY_BASE : PCIEPHY_BASE)
-#define SGMIIPHY_ADDR(l, a)            \
-       ((void __iomem *)(((a & 0x00007FF) * 2) + SGMIIPHY_BASE(l)))
-
-#define phy_read16(l, a)       read16((void __iomem *)SGMIIPHY_ADDR(l, a))
-#define phy_write16(l, a, data, mask)  \
-       reg_set16(SGMIIPHY_ADDR(l, a), data, mask)
+static inline void __iomem *sgmiiphy_addr(u32 lane, u32 addr)
+{
+       addr = (addr & 0x00007FF) * 2;
+       if (lane == 1)
+               return PCIEPHY_BASE + addr;
+       else
+               return USB3PHY_BASE + addr;
+}
 
 /* units */
 #define PCIE                           1