ARM: dts: stm32: DT alignment with kernel v5.4-rc4
authorPatrick Delaunay <patrick.delaunay@st.com>
Wed, 6 Nov 2019 15:16:33 +0000 (16:16 +0100)
committerPatrick Delaunay <patrick.delaunay@st.com>
Tue, 26 Nov 2019 09:11:48 +0000 (10:11 +0100)
Device tree and binding alignment with kernel v5.4-rc4

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
12 files changed:
arch/arm/dts/st-pincfg.h
arch/arm/dts/stm32429i-eval.dts
arch/arm/dts/stm32f429.dtsi
arch/arm/dts/stm32f746.dtsi
arch/arm/dts/stm32h743i-eval.dts
arch/arm/dts/stm32mp157-pinctrl.dtsi
arch/arm/dts/stm32mp157a-dk1.dts
arch/arm/dts/stm32mp157c-ed1.dts
arch/arm/dts/stm32mp157c-ev1.dts
arch/arm/dts/stm32mp157c.dtsi
include/dt-bindings/mfd/stm32f7-rcc.h
include/dt-bindings/mfd/stm32h7-rcc.h

index 4851c387d52dfa843ed9eff81e5e098146854d27..d80551202292457fc38881a471cddad49c611e02 100644 (file)
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 #ifndef _ST_PINCFG_H_
 #define _ST_PINCFG_H_
 
index bd41ae3c142b2421c2c5e21cd38d1af09dae2ca7..c5afa0c1620fb0d31e533310ad6e7854841c34e5 100644 (file)
                dma-ranges = <0xc0000000 0x0 0x10000000>;
        };
 
-       regulators {
-               compatible = "simple-bus";
-               #address-cells = <1>;
-               #size-cells = <0>;
+       vdda: regulator-vdda {
+               compatible = "regulator-fixed";
+               regulator-name = "vdda";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
 
-               reg_vref: regulator@0 {
-                       compatible = "regulator-fixed";
-                       reg = <0>;
-                       regulator-name = "vref";
-                       regulator-min-microvolt = <3300000>;
-                       regulator-max-microvolt = <3300000>;
-               };
+       vref: regulator-vref {
+               compatible = "regulator-fixed";
+               regulator-name = "vref";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
        };
 
        leds {
 &adc {
        pinctrl-names = "default";
        pinctrl-0 = <&adc3_in8_pin>;
-       vref-supply = <&reg_vref>;
+       vdda-supply = <&vdda>;
+       vref-supply = <&vref>;
        status = "okay";
        adc3: adc@200 {
                st,adc-channels = <8>;
index ec84ae4f527c12a9b84904c3c9646bfe19ae2900..db0b82e89ea3c16e66839588fbcddabc9c7d6d7b 100644 (file)
@@ -71,6 +71,7 @@
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
                };
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
                };
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
                };
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
                };
index 66360cf21c1ed44ea99d3a2d72d460d52200d4f6..3f312ab3a775245f1ccb7e785ec3aaf0c89e387f 100644 (file)
@@ -58,6 +58,7 @@
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
@@ -87,6 +88,7 @@
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
                };
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
                };
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
                };
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
                };
index ab78ad53237557066680ab48d2e384680f8646a0..e4d3c58f3d97b735e929354c0fa036feeea50667 100644 (file)
@@ -87,6 +87,7 @@
 };
 
 &adc_12 {
+       vdda-supply = <&vdda>;
        vref-supply = <&vdda>;
        status = "okay";
        adc1: adc@0 {
index 4367e8dcf7584f936dfebc2af348c452bf0e33bf..2d73d502d9e5ee4c03193bb1878e50ec25f8b34a 100644 (file)
                                };
                        };
 
-                       m_can1_sleep_pins_a: m_can1-sleep@0 {
+                       m_can1_sleep_pins_a: m_can1-sleep-0 {
                                pins {
                                        pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
                                                 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
index c210acc0aa22c2bc73facb9837c9a2d65f918323..46522530128c8cd7a55583064ebf9d876e966345 100644 (file)
                #size-cells = <1>;
                ranges;
 
+               mcuram2: mcuram2@10000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x10000000 0x40000>;
+                       no-map;
+               };
+
+               vdev0vring0: vdev0vring0@10040000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x10040000 0x1000>;
+                       no-map;
+               };
+
+               vdev0vring1: vdev0vring1@10041000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x10041000 0x1000>;
+                       no-map;
+               };
+
+               vdev0buffer: vdev0buffer@10042000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x10042000 0x4000>;
+                       no-map;
+               };
+
+               mcuram: mcuram@30000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x30000000 0x40000>;
+                       no-map;
+               };
+
+               retram: retram@38000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x38000000 0x10000>;
+                       no-map;
+               };
+
                gpu_reserved: gpu@d4000000 {
                        reg = <0xd4000000 0x4000000>;
                        no-map;
                        default-state = "off";
                };
        };
+
+       sound {
+               compatible = "audio-graph-card";
+               label = "STM32MP1-DK";
+               routing =
+                       "Playback" , "MCLK",
+                       "Capture" , "MCLK",
+                       "MICL" , "Mic Bias";
+               dais = <&sai2a_port &sai2b_port>;
+               status = "okay";
+       };
 };
 
 &cec {
                        };
                };
        };
+
+       cs42l51: cs42l51@4a {
+               compatible = "cirrus,cs42l51";
+               reg = <0x4a>;
+               #sound-dai-cells = <0>;
+               VL-supply = <&v3v3>;
+               VD-supply = <&v1v8_audio>;
+               VA-supply = <&v1v8_audio>;
+               VAHP-supply = <&v1v8_audio>;
+               reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
+               clocks = <&sai2a>;
+               clock-names = "MCLK";
+               status = "okay";
+
+               cs42l51_port: port {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       cs42l51_tx_endpoint: endpoint@0 {
+                               reg = <0>;
+                               remote-endpoint = <&sai2a_endpoint>;
+                               frame-master;
+                               bitclock-master;
+                       };
+
+                       cs42l51_rx_endpoint: endpoint@1 {
+                               reg = <1>;
+                               remote-endpoint = <&sai2b_endpoint>;
+                               frame-master;
+                               bitclock-master;
+                       };
+               };
+       };
 };
 
 &i2c4 {
 };
 
 &m4_rproc {
+       memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+                       <&vdev0vring1>, <&vdev0buffer>;
        mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
        mbox-names = "vq0", "vq1", "shutdown";
+       interrupt-parent = <&exti>;
+       interrupts = <68 1>;
        status = "okay";
 };
 
        status = "okay";
 };
 
+&sai2 {
+       clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+       clock-names = "pclk", "x8k", "x11k";
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
+       pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>;
+       status = "okay";
+
+       sai2a: audio-controller@4400b004 {
+               #clock-cells = <0>;
+               dma-names = "tx";
+               clocks = <&rcc SAI2_K>;
+               clock-names = "sai_ck";
+               status = "okay";
+
+               sai2a_port: port {
+                       sai2a_endpoint: endpoint {
+                               remote-endpoint = <&cs42l51_tx_endpoint>;
+                               format = "i2s";
+                               mclk-fs = <256>;
+                               dai-tdm-slot-num = <2>;
+                               dai-tdm-slot-width = <32>;
+                       };
+               };
+       };
+
+       sai2b: audio-controller@4400b024 {
+               dma-names = "rx";
+               st,sync = <&sai2a 2>;
+               clocks = <&rcc SAI2_K>, <&sai2a>;
+               clock-names = "sai_ck", "MCLK";
+               status = "okay";
+
+               sai2b_port: port {
+                       sai2b_endpoint: endpoint {
+                               remote-endpoint = <&cs42l51_rx_endpoint>;
+                               format = "i2s";
+                               mclk-fs = <256>;
+                               dai-tdm-slot-num = <2>;
+                               dai-tdm-slot-width = <32>;
+                       };
+               };
+       };
+};
+
 &sdmmc1 {
        pinctrl-names = "default", "opendrain", "sleep";
        pinctrl-0 = <&sdmmc1_b4_pins_a>;
index 66deca1bc9ca4754087851212d8bc17e53ab9987..73d07cf42f1c19633639570b1b45559cfad572ec 100644 (file)
                #size-cells = <1>;
                ranges;
 
+               mcuram2: mcuram2@10000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x10000000 0x40000>;
+                       no-map;
+               };
+
+               vdev0vring0: vdev0vring0@10040000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x10040000 0x1000>;
+                       no-map;
+               };
+
+               vdev0vring1: vdev0vring1@10041000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x10041000 0x1000>;
+                       no-map;
+               };
+
+               vdev0buffer: vdev0buffer@10042000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x10042000 0x4000>;
+                       no-map;
+               };
+
+               mcuram: mcuram@30000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x30000000 0x40000>;
+                       no-map;
+               };
+
+               retram: retram@38000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x38000000 0x10000>;
+                       no-map;
+               };
+
                gpu_reserved: gpu@e8000000 {
                        reg = <0xe8000000 0x8000000>;
                        no-map;
 };
 
 &m4_rproc {
+       memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+                       <&vdev0vring1>, <&vdev0buffer>;
        mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
        mbox-names = "vq0", "vq1", "shutdown";
+       interrupt-parent = <&exti>;
+       interrupts = <68 1>;
        status = "okay";
 };
 
index 23de232831c0405fb9c4814ddb5f18bbd73cc789..89d29b50c3f46df13ba252fa914aee8de50a0dfc 100644 (file)
 &dsi {
        #address-cells = <1>;
        #size-cells = <0>;
+       phy-dsi-supply = <&reg18>;
        status = "okay";
 
        ports {
        #address-cells = <1>;
        #size-cells = <0>;
 
-       nand: nand@0 {
+       nand@0 {
                reg = <0>;
                nand-on-flash-bbt;
                #address-cells = <1>;
index a6045dd682c6900dce9757593690d7e1c59f5aed..6c670cf9a362adfbc4c0e3b408b66155c326b27f 100644 (file)
                };
        };
 
+       booster: regulator-booster {
+               compatible = "st,stm32mp1-booster";
+               st,syscfg = <&syscfg>;
+               status = "disabled";
+       };
+
        reboot {
                compatible = "syscon-reboot";
                regmap = <&rcc>;
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
                        timer@15 {
 
                        pwm {
                                compatible = "st,stm32-pwm";
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
                        clocks = <&rcc ADC12>, <&rcc ADC12_K>;
                        clock-names = "bus", "adc";
                        interrupt-controller;
+                       st,syscfg = <&syscfg>;
                        #interrupt-cells = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                              <0x89010000 0x1000>,
                              <0x89020000 0x1000>;
                        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+                       dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
+                              <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
+                              <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
+                       dma-names = "tx", "rx", "ecc";
                        clocks = <&rcc FMC_K>;
                        resets = <&rcc FMC_R>;
                        status = "disabled";
                        reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
                        reg-names = "qspi", "qspi_mm";
                        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+                       dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
+                              <&mdma1 22 0x10 0x100008 0x0 0x0>;
+                       dma-names = "tx", "rx";
                        clocks = <&rcc QSPI_K>;
                        resets = <&rcc QSPI_R>;
                        status = "disabled";
index c9087f5f3dac0a990f01300c298b6b19fbada88c..ba5cb7456ee4a6122e8b593af326262320c4ffe4 100644 (file)
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * This header provides constants for the STM32F7 RCC IP
  */
index b96b3c3ac1ab39fbed9c0788152c99d7822789d4..06e8476bf08f4b623a80dce1406d10cb3b0aa5d2 100644 (file)
@@ -12,6 +12,7 @@
 #define STM32H7_RCC_AHB3_FMC           12
 #define STM32H7_RCC_AHB3_QUADSPI       14
 #define STM32H7_RCC_AHB3_SDMMC1                16
+#define STM32H7_RCC_AHB3_CPU           31
 #define STM32H7_RCC_AHB3_CPU1          31
 
 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
@@ -56,7 +57,6 @@
 
 #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
 
-
 /* APB3 */
 #define STM32H7_RCC_APB3_LTDC          3
 #define STM32H7_RCC_APB3_DSI           4