#include <common.h>
#include <fdtdec.h>
#include <asm/io.h>
+#include <i2c.h>
#include <media_bus_format.h>
#include "dw_hdmi.h"
u32 trytime = 5;
u32 n;
+ if (CONFIG_IS_ENABLED(DM_I2C) && hdmi->ddc_bus) {
+ struct udevice *chip;
+
+ edid_read_err = i2c_get_chip(hdmi->ddc_bus,
+ HDMI_I2CM_SLAVE_DDC_ADDR,
+ 1, &chip);
+ if (edid_read_err)
+ return edid_read_err;
+
+ return dm_i2c_read(chip, shift, buff, HDMI_EDID_BLOCK_SIZE);
+ }
+
/* set ddc i2c clk which devided from ddc_clk to 100khz */
hdmi_write(hdmi, hdmi->i2c_clk_high, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
hdmi_write(hdmi, hdmi->i2c_clk_low, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
}
#endif
+ uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
+ &priv->hdmi.ddc_bus);
+
ret = reset_get_bulk(dev, &resets);
if (ret)
return ret;
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
+ &hdmi->ddc_bus);
+
return 0;
}
priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
priv->mux = uc_plat->source_id;
+ uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
+ &priv->hdmi.ddc_bus);
+
dw_hdmi_init(&priv->hdmi);
return 0;
u8 i2c_clk_low;
u8 reg_io_width;
struct hdmi_data_info hdmi_data;
+ struct udevice *ddc_bus;
int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset);