EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0

MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index f7829b2cc76a9ff4f7aaabe607028201335f947f..366c35ae0841d308e4cb7862bd655e7f58125460 100644 (file)
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
        struct exynos5_clock *clk =
                (struct exynos5_clock *)samsung_get_base_clock();
        unsigned long r, m, p, s, k = 0, mask, fout;
-       unsigned int freq;
+       unsigned int freq, pll_div2_sel,  mpll_fout_sel;
 
        switch (pllreg) {
        case APLL:
@@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
                fout = m * (freq / (p * (1 << (s - 1))));
        }
 
+       /* According to the user manual, in EVT1 MPLL always gives
+        * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
+       if (pllreg == MPLL) {
+               pll_div2_sel = readl(&clk->pll_div2_sel);
+               mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
+                               & MPLL_FOUT_SEL_MASK;
+               if (mpll_fout_sel == 0)
+                       fout /= 2;
+       }
+
        return fout;
 }
 

diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
index 90271f1a489c70676be6cec711ae7db19effb1ec..bf41c1959f136e0f26a824212355c428145db83c 100644 (file)
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -596,4 +596,7 @@ struct exynos5_clock {
        unsigned char   res123[0xf5d8];
 };
 #endif
+
+#define MPLL_FOUT_SEL_SHIFT    4
+#define MPLL_FOUT_SEL_MASK     0x1
 #endif