powerpc/83xx/km: merge tuxa and tuda1 boards to tuxx1
authorHolger Brunck <holger.brunck@keymile.com>
Wed, 14 Dec 2011 15:21:44 +0000 (16:21 +0100)
committerKim Phillips <kim.phillips@freescale.com>
Tue, 10 Jan 2012 02:10:33 +0000 (20:10 -0600)
These boards are from a u-boot point of view identical. So collect
the two headerfiles to one, to decrease maintenance.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
MAINTAINERS
boards.cfg
include/configs/tuda1.h [deleted file]
include/configs/tuxa1.h [deleted file]
include/configs/tuxx1.h [new file with mode: 0644]

index 4bf12b5c4fbe07187169f81ae8e400a4a629796d..5cb70b0fa611570a2403622baa6de3542d1431e1 100644 (file)
@@ -436,11 +436,12 @@ Heiko Schocher <hs@denx.de>
        municse         MPC5200
        sc3             PPC405GP
        suvd3           MPC8321
-       tuda1           MPC8321
-       tuxa1           MPC8321
        uc101           MPC5200
        ve8313          MPC8313
 
+Holger Brunck <holger.brunck@keymile.com>
+       tuxx1           MPC8321
+
 Peter De Schrijver <p2@mind.be>
 
        ML2             PPC4xx
index 0b325329fb66ebcaa45873bbe690b0a69e3de413..0eeb4c799d13ea1cdb8f9142230229a688f94fc5 100644 (file)
@@ -593,8 +593,7 @@ MPC837XERDB                  powerpc     mpc83xx     mpc837xerdb         freesca
 kmeter1                      powerpc     mpc83xx     km83xx              keymile
 kmsupx5                      powerpc     mpc83xx     km83xx              keymile
 suvd3                        powerpc     mpc83xx     km83xx              keymile
-tuda1                        powerpc     mpc83xx     km83xx              keymile
-tuxa1                        powerpc     mpc83xx     km83xx              keymile
+tuxx1                        powerpc     mpc83xx     km83xx              keymile
 MERGERBOX                    powerpc     mpc83xx     mergerbox           matrix_vision
 MVBLM7                       powerpc     mpc83xx     mvblm7              matrix_vision
 SIMPC8313_LP                 powerpc     mpc83xx     simpc8313           sheldon        -           SIMPC8313:NAND_LP
diff --git a/include/configs/tuda1.h b/include/configs/tuda1.h
deleted file mode 100644 (file)
index 2581d8a..0000000
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *                    Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- *                    Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- *                    Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * (C) Copyright 2008
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * (C) Copyright 2010-2011
- * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TUDA1           /* TUDA1 board specific */
-#define CONFIG_HOSTNAME                tuda1
-#define CONFIG_KM_BOARD_NAME   "tuda1"
-
-#define        CONFIG_SYS_TEXT_BASE    0xF0000000
-
-/* include common defines/options for all 8321 Keymile boards */
-#include "km/km8321-common.h"
-
-#define CONFIG_SYS_APP1_BASE   0xA0000000    /* PAXG */
-#define        CONFIG_SYS_APP1_SIZE    256 /* Megabytes */
-#define CONFIG_SYS_APP2_BASE   0xB0000000    /* PINC3 */
-#define        CONFIG_SYS_APP2_SIZE    256 /* Megabytes */
-
-/*
- * Init Local Bus Memory Controller:
- *
- * Bank Bus     Machine PortSz  Size  Device
- * ---- ---     ------- ------  -----  ------
- *  2   Local   GPCM    8 bit  256MB   PAXG
- *  3   Local   GPCM    8 bit  256MB   PINC3
- *
- */
-
-/*
- * PAXG on the local bus CS2
- */
-/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM    CONFIG_SYS_APP1_BASE
-/* Window size: 256 MB */
-#define CONFIG_SYS_LBLAWAR2_PRELIM     (LBLAWAR_EN | LBLAWAR_256MB)
-
-#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_APP1_BASE | \
-                                BR_PS_8 | \
-                                BR_MS_GPCM | \
-                                BR_V)
-
-#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
-                                OR_GPCM_CSNT | \
-                                OR_GPCM_ACS_DIV4 | \
-                                OR_GPCM_SCY_2 | \
-                                OR_GPCM_TRLX_SET | \
-                                OR_GPCM_EHTR_CLEAR | \
-                                OR_GPCM_EAD)
-/*
- * PINC3 on the local bus CS3
- */
-/* Access window base at PINC3 base */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM    CONFIG_SYS_APP2_BASE
-/* Window size: 256 MB */
-#define CONFIG_SYS_LBLAWAR3_PRELIM     (LBLAWAR_EN | LBLAWAR_256MB)
-
-#define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_APP2_BASE | \
-                                BR_PS_8 |              \
-                                BR_MS_GPCM |           \
-                                BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
-                                OR_GPCM_CSNT | \
-                                OR_GPCM_ACS_DIV2 | \
-                                OR_GPCM_SCY_2 | \
-                                OR_GPCM_TRLX_SET | \
-                                OR_GPCM_EHTR_CLEAR)
-
-#define CONFIG_SYS_MAMR                (MxMR_GPL_x4DIS | \
-                                0x0000c000 | \
-                                MxMR_WLFx_2X)
-
-/*
- * MMU Setup
- */
-/* PAXG:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L      (CONFIG_SYS_APP1_BASE | \
-                                BATL_PP_RW | \
-                                BATL_MEMCOHERENCE)
-/* 512M should also include APP2... */
-#define CONFIG_SYS_IBAT5U      (CONFIG_SYS_APP1_BASE | \
-                                BATU_BL_256M | \
-                                BATU_VS | \
-                                BATU_VP)
-#define CONFIG_SYS_DBAT5L      (CONFIG_SYS_APP1_BASE | \
-                                BATL_PP_RW | \
-                                BATL_CACHEINHIBIT | \
-                                BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U      CONFIG_SYS_IBAT5U
-
-/* PINC3:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT6L      (CONFIG_SYS_APP2_BASE | \
-                                BATL_PP_RW | \
-                                BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U      (CONFIG_SYS_APP2_BASE | \
-                                BATU_BL_256M | \
-                                BATU_VS | \
-                                BATU_VP)
-#define CONFIG_SYS_DBAT6L      (CONFIG_SYS_APP2_BASE | \
-                                BATL_PP_RW | \
-                                BATL_CACHEINHIBIT | \
-                                BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U      CONFIG_SYS_IBAT6U
-
-#define CONFIG_SYS_IBAT7L      (0)
-#define CONFIG_SYS_IBAT7U      (0)
-#define CONFIG_SYS_DBAT7L      CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U      CONFIG_SYS_IBAT7U
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h
deleted file mode 100644 (file)
index 2d9af3f..0000000
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *                    Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- *                    Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- *                    Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * (C) Copyright 2008
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * (C) Copyright 2010
- * Yan Bin, Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TUXA1           /* TUXA1 board specific */
-#define CONFIG_HOSTNAME                tuxa1
-#define CONFIG_KM_BOARD_NAME   "tuxa1"
-
-#define        CONFIG_SYS_TEXT_BASE    0xF0000000
-
-/* include common defines/options for all 8321 Keymile boards */
-#include "km/km8321-common.h"
-
-#define        CONFIG_SYS_LPXF_BASE            0xA0000000    /* LPXF */
-#define        CONFIG_SYS_LPXF_SIZE            256 /* Megabytes */
-#define        CONFIG_SYS_PINC2_BASE           0xB0000000    /* PINC2 */
-#define        CONFIG_SYS_PINC2_SIZE           256 /* Megabytes */
-
-/*
- * Init Local Bus Memory Controller:
- *
- * Bank Bus     Machine PortSz  Size  Device
- * ---- ---     ------- ------  -----  ------
- *  2   Local   GPCM    8 bit  256MB   LPXF
- *  3   Local   GPCM    8 bit  256MB   PINC2
- *
- */
-
-/*
- * LPXF on the local bus CS2
- * Window base at flash base
- * Window size: 256 MB
- */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM    CONFIG_SYS_LPXF_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM     (LBLAWAR_EN | LBLAWAR_256MB)
-
-#define CONFIG_SYS_BR2_PRELIM       (CONFIG_SYS_LPXF_BASE | \
-                               BR_PS_8 | \
-                               BR_MS_GPCM | \
-                               BR_V)
-
-#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \
-                                OR_GPCM_CSNT | \
-                                OR_GPCM_ACS_DIV4 | \
-                                OR_GPCM_SCY_2 | \
-                                OR_GPCM_TRLX_SET | \
-                                OR_GPCM_EHTR_CLEAR | \
-                                OR_GPCM_EAD)
-/*
- * PINC2 on the local bus CS3
- * Access window base at PINC2 base
- * Window size: 256 MB
- */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM    CONFIG_SYS_PINC2_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM     (LBLAWAR_EN | LBLAWAR_256MB)
-
-#define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_PINC2_BASE | \
-                                BR_PS_8 | \
-                                BR_MS_GPCM | \
-                                BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM  (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \
-                                OR_GPCM_CSNT | \
-                                OR_GPCM_ACS_DIV2 | \
-                                OR_GPCM_SCY_2 | \
-                                OR_GPCM_TRLX_SET | \
-                                OR_GPCM_EHTR_CLEAR)
-
-#define CONFIG_SYS_MAMR                (MxMR_GPL_x4DIS | \
-                                0x0000c000 | \
-                                MxMR_WLFx_2X)
-
-/*
- * MMU Setup
- */
-/* LPXF:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L      (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \
-                                BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U      (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \
-                                BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L      (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \
-                                BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U      CONFIG_SYS_IBAT5U
-
-/* PINC2:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT6L      (CONFIG_SYS_PINC2_BASE | BATL_PP_RW | \
-                                BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U      (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \
-                                BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L      (CONFIG_SYS_PINC2_BASE | BATL_PP_RW | \
-                                BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U      CONFIG_SYS_IBAT6U
-
-#define CONFIG_SYS_IBAT7L      (0)
-#define CONFIG_SYS_IBAT7U      (0)
-#define CONFIG_SYS_DBAT7L      CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U      CONFIG_SYS_IBAT7U
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h
new file mode 100644 (file)
index 0000000..b07f6b3
--- /dev/null
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010-2011
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ * Holger Brunck,  Keymile GmbH, holger.bruncl@keymile.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_TUXXX           /* TUXX1 board specific */
+#define CONFIG_HOSTNAME                tuxx1
+#define CONFIG_KM_BOARD_NAME   "tuxx1"
+
+#define        CONFIG_SYS_TEXT_BASE    0xF0000000
+
+/* include common defines/options for all 8321 Keymile boards */
+#include "km/km8321-common.h"
+
+#define CONFIG_SYS_APP1_BASE   0xA0000000    /* PAXG */
+#define        CONFIG_SYS_APP1_SIZE    256 /* Megabytes */
+#define CONFIG_SYS_APP2_BASE   0xB0000000    /* PINC3 */
+#define        CONFIG_SYS_APP2_SIZE    256 /* Megabytes */
+
+/*
+ * Init Local Bus Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Size  Device on TUDA1  TUXA1
+ * ---- ---     ------- ------  -----  ---------------------
+ *  2   Local   GPCM    8 bit  256MB            PAXG  LPXF
+ *  3   Local   GPCM    8 bit  256MB            PINC3 PINC2
+ *
+ */
+
+/*
+ * Configuration for C2 on the local bus
+ */
+/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM    CONFIG_SYS_APP1_BASE
+/* Window size: 256 MB */
+#define CONFIG_SYS_LBLAWAR2_PRELIM     (LBLAWAR_EN | LBLAWAR_256MB)
+
+#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_APP1_BASE | \
+                                BR_PS_8 | \
+                                BR_MS_GPCM | \
+                                BR_V)
+
+#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
+                                OR_GPCM_CSNT | \
+                                OR_GPCM_ACS_DIV4 | \
+                                OR_GPCM_SCY_2 | \
+                                OR_GPCM_TRLX_SET | \
+                                OR_GPCM_EHTR_CLEAR | \
+                                OR_GPCM_EAD)
+/*
+ * Configuration for C3 on the local bus
+ */
+/* Access window base at PINC3 base */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM    CONFIG_SYS_APP2_BASE
+/* Window size: 256 MB */
+#define CONFIG_SYS_LBLAWAR3_PRELIM     (LBLAWAR_EN | LBLAWAR_256MB)
+
+#define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_APP2_BASE | \
+                                BR_PS_8 |              \
+                                BR_MS_GPCM |           \
+                                BR_V)
+
+#define CONFIG_SYS_OR3_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+                                OR_GPCM_CSNT | \
+                                OR_GPCM_ACS_DIV2 | \
+                                OR_GPCM_SCY_2 | \
+                                OR_GPCM_TRLX_SET | \
+                                OR_GPCM_EHTR_CLEAR)
+
+#define CONFIG_SYS_MAMR                (MxMR_GPL_x4DIS | \
+                                0x0000c000 | \
+                                MxMR_WLFx_2X)
+
+/*
+ * MMU Setup
+ */
+/* APP1: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT5L      (CONFIG_SYS_APP1_BASE | \
+                                BATL_PP_RW | \
+                                BATL_MEMCOHERENCE)
+/* 512M should also include APP2... */
+#define CONFIG_SYS_IBAT5U      (CONFIG_SYS_APP1_BASE | \
+                                BATU_BL_256M | \
+                                BATU_VS | \
+                                BATU_VP)
+#define CONFIG_SYS_DBAT5L      (CONFIG_SYS_APP1_BASE | \
+                                BATL_PP_RW | \
+                                BATL_CACHEINHIBIT | \
+                                BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT5U      CONFIG_SYS_IBAT5U
+
+/* APP2:  icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT6L      (CONFIG_SYS_APP2_BASE | \
+                                BATL_PP_RW | \
+                                BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U      (CONFIG_SYS_APP2_BASE | \
+                                BATU_BL_256M | \
+                                BATU_VS | \
+                                BATU_VP)
+#define CONFIG_SYS_DBAT6L      (CONFIG_SYS_APP2_BASE | \
+                                BATL_PP_RW | \
+                                BATL_CACHEINHIBIT | \
+                                BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U      CONFIG_SYS_IBAT6U
+
+#define CONFIG_SYS_IBAT7L      (0)
+#define CONFIG_SYS_IBAT7U      (0)
+#define CONFIG_SYS_DBAT7L      CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U      CONFIG_SYS_IBAT7U
+
+#endif /* __CONFIG_H */