MIPS: cache: make index base address configurable

The index base address used for the cache initialisation is currently
hard-coded to CKSEG0. Make this value configurable if a MIPS system
needs to have a different address (e.g. in SRAM or ScratchPad RAM).

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f71597f6dac483561bbe96669d6791e93e2b2936..30fb9bff748f8b25e43ef12fa072980fdfad3c22 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -219,6 +219,18 @@ config MIPS_CM_BASE
          the GCRs occupy a region of the physical address space which is
          otherwise unused, or at minimum that software doesn't need to access.
 
+config MIPS_CACHE_INDEX_BASE
+       hex "Index base address for cache initialisation"
+       default 0x80000000 if CPU_MIPS32
+       default 0xffffffff80000000 if CPU_MIPS64
+       help
+         This is the base address for a memory block, which is used for
+         initialising the cache lines. This is also the base address of a memory
+         block which is used for loading and filling cache lines when
+         SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
+         Normally this is CKSEG0. If the MIPS system needs to move this block
+         to some SRAM or ScratchPad RAM, adapt this option accordingly.
+
 endmenu
 
 menu "OS boot interface"

diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 4e956031b3ca20db6e646b9fe4dec60cab3f4b56..5616ee6dfd6efb5d3b70ba103a72a411e63c510a 100644 (file)
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -18,8 +18,6 @@
 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
 #endif
 
-#define INDEX_BASE     CKSEG0
-
        .macro  f_fill64 dst, offset, val
        LONG_S  \val, (\offset +  0 * LONGSIZE)(\dst)
        LONG_S  \val, (\offset +  1 * LONGSIZE)(\dst)
@@ -256,7 +254,7 @@ l2_probe_done:
        /*
         * Now clear that much memory starting from zero.
         */
-       PTR_LI          a0, CKSEG1
+       PTR_LI          a0, CKSEG1ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
        PTR_ADDU        a1, a0, v0
 2:     PTR_ADDIU       a0, 64
        f_fill64        a0, -64, zero
@@ -272,7 +270,7 @@ l2_probe_done:
        bnez            R_L2_BYPASSED, l1_init
 
 l2_init:
-       PTR_LI          t0, INDEX_BASE
+       PTR_LI          t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
        PTR_ADDU        t1, t0, R_L2_SIZE
 1:     cache           INDEX_STORE_TAG_SD, 0(t0)
        PTR_ADDU        t0, t0, R_L2_LINE
@@ -308,16 +306,16 @@ l1_init:
         * Initialize the I-cache first,
         */
        blez            R_IC_SIZE, 1f
-       PTR_LI          t0, INDEX_BASE
+       PTR_LI          t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
        PTR_ADDU        t1, t0, R_IC_SIZE
        /* clear tag to invalidate */
        cache_loop      t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
 #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
        /* fill once, so data field parity is correct */
-       PTR_LI          t0, INDEX_BASE
+       PTR_LI          t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
        cache_loop      t0, t1, R_IC_LINE, FILL
        /* invalidate again - prudent but not strictly neccessary */
-       PTR_LI          t0, INDEX_BASE
+       PTR_LI          t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
        cache_loop      t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
 #endif
        sync
@@ -340,18 +338,18 @@ l1_init:
         * then initialize D-cache.
         */
 1:     blez            R_DC_SIZE, 3f
-       PTR_LI          t0, INDEX_BASE
+       PTR_LI          t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
        PTR_ADDU        t1, t0, R_DC_SIZE
        /* clear all tags */
        cache_loop      t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
 #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
        /* load from each line (in cached space) */
-       PTR_LI          t0, INDEX_BASE
+       PTR_LI          t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
 2:     LONG_L          zero, 0(t0)
        PTR_ADDU        t0, R_DC_LINE
        bne             t0, t1, 2b
        /* clear all tags */
-       PTR_LI          t0, INDEX_BASE
+       PTR_LI          t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
        cache_loop      t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
 #endif
 3: