rockchip: sdram_common: add common dram_init_banksize
authorKever Yang <kever.yang@rock-chips.com>
Mon, 22 Jul 2019 12:02:02 +0000 (20:02 +0800)
committerKever Yang <kever.yang@rock-chips.com>
Mon, 29 Jul 2019 02:26:28 +0000 (10:26 +0800)
dram_init_banksize() can be common used by all SoCs, move it into
sdram_common.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
arch/arm/mach-rockchip/rk3128-board.c
arch/arm/mach-rockchip/rk3128/rk3128.c
arch/arm/mach-rockchip/rk322x-board.c
arch/arm/mach-rockchip/rk3288/rk3288.c
arch/arm/mach-rockchip/rk3328/rk3328.c
arch/arm/mach-rockchip/rk3368/rk3368.c
arch/arm/mach-rockchip/rk3399/rk3399.c
arch/arm/mach-rockchip/sdram_common.c
board/rockchip/evb_rv1108/evb_rv1108.c

index cfc41286e74149d2449bfa6190891eed13b820c0..b931057329f969b8642b555839a5c4e1d158d369 100644 (file)
@@ -41,19 +41,6 @@ int board_init(void)
        return 0;
 }
 
-int dram_init_banksize(void)
-{
-       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-       gd->bd->bi_dram[0].size = 0x8400000;
-       /* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */
-       gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
-                               + gd->bd->bi_dram[0].size + 0xe00000;
-       gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
-                               + gd->ram_size - gd->bd->bi_dram[1].start;
-
-       return 0;
-}
-
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
index 11bba148c33f824bf5842f96d1390ab4304ec552..ee176de80b06f810099bbad601e73a22b783930f 100644 (file)
@@ -2,6 +2,9 @@
 /*
  * Copyright (c) 2017 Rockchip Electronics Co., Ltd
  */
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 int arch_cpu_init(void)
 {
index 5103ad4ccc7096b57be4c60f935ae9a04816e939..91fbd6abb8eae0cf20b62ac40d497f3b25912606 100644 (file)
@@ -45,19 +45,6 @@ int board_init(void)
        return 0;
 }
 
-int dram_init_banksize(void)
-{
-       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-       gd->bd->bi_dram[0].size = 0x8400000;
-       /* Reserve 0x200000 for OPTEE */
-       gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
-                               + gd->bd->bi_dram[0].size + 0x200000;
-       gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
-                               + gd->ram_size - gd->bd->bi_dram[1].start;
-
-       return 0;
-}
-
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
index 04a87d64f44808b5840dbd3ae1ff3d3b5f6b596c..b80193012adfe3bcdc9122b0b2567caba747f0c1 100644 (file)
@@ -67,18 +67,3 @@ void board_debug_uart_init(void)
                     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
 }
 #endif
-
-#ifdef CONFIG_SPL_OS_BOOT
-
-#define PMU_BASE               0xff730000
-int dram_init_banksize(void)
-{
-       struct rk3288_pmu *const pmu = (void *)PMU_BASE;
-       size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]);
-
-       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-       gd->bd->bi_dram[0].size = size;
-
-       return 0;
-}
-#endif
index afd9de4a1ff15ff889b4a42925626565853598a8..592f287613bfc0c682b1ebc00de07db72777f0e3 100644 (file)
@@ -44,17 +44,6 @@ static struct mm_region rk3328_mem_map[] = {
 
 struct mm_region *mem_map = rk3328_mem_map;
 
-int dram_init_banksize(void)
-{
-       size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
-
-       /* Reserve 0x200000 for ATF bl31 */
-       gd->bd->bi_dram[0].start = 0x200000;
-       gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
-
-       return 0;
-}
-
 int arch_cpu_init(void)
 {
        /* We do some SoC one time setting here. */
index c75a5cd0c44cd5c7e25998441682d7ccd442d20b..7ccd417a18ce6ea54751d3121b3f22384d1090e4 100644 (file)
@@ -58,17 +58,6 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
        [BROM_BOOTSOURCE_SD] = "dwmmc@ff0c0000",
 };
 
-int dram_init_banksize(void)
-{
-       size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
-
-       /* Reserve 0x200000 for ATF bl31 */
-       gd->bd->bi_dram[0].start = 0x200000;
-       gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
-
-       return 0;
-}
-
 #ifdef CONFIG_ARCH_EARLY_INIT_R
 static int mcu_init(void)
 {
index 89c4d592671d9dc8e4aedfceb23d48dd815c4424..863024d0710c11d20b1d3c9a1bedf433deb6e0b4 100644 (file)
@@ -78,17 +78,6 @@ void rockchip_stimer_init(void)
 }
 #endif
 
-int dram_init_banksize(void)
-{
-       size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
-
-       /* Reserve 0x200000 for ATF bl31 */
-       gd->bd->bi_dram[0].start = 0x200000;
-       gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
-
-       return 0;
-}
-
 int arch_cpu_init(void)
 {
 
index 8684dbd4fa67fca7691a4f523e0ccc648ec2d53a..22a4aca9402a9684d16d844cdde5f425d1a1e83a 100644 (file)
 #include <dm/uclass-internal.h>
 
 DECLARE_GLOBAL_DATA_PTR;
+
+#define TRUST_PARAMETER_OFFSET    (34 * 1024 * 1024)
+
+struct tos_parameter_t {
+       u32 version;
+       u32 checksum;
+       struct {
+               char name[8];
+               s64 phy_addr;
+               u32 size;
+               u32 flags;
+       } tee_mem;
+       struct {
+               char name[8];
+               s64 phy_addr;
+               u32 size;
+               u32 flags;
+       } drm_mem;
+       s64 reserve[8];
+};
+
+int dram_init_banksize(void)
+{
+       size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
+                        gd->ram_top);
+
+#ifdef CONFIG_ARM64
+       /* Reserve 0x200000 for ATF bl31 */
+       gd->bd->bi_dram[0].start = 0x200000;
+       gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
+#else
+#ifdef CONFIG_SPL_OPTEE
+       struct tos_parameter_t *tos_parameter;
+
+       tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
+                       TRUST_PARAMETER_OFFSET);
+
+       if (tos_parameter->tee_mem.flags == 1) {
+               gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+               gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
+                                       - CONFIG_SYS_SDRAM_BASE;
+               gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
+                                       tos_parameter->tee_mem.size;
+               gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+                                       + top - gd->bd->bi_dram[1].start;
+       } else {
+               gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+               gd->bd->bi_dram[0].size = 0x8400000;
+               /* Reserve 32M for OPTEE with TA */
+               gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+                                       + gd->bd->bi_dram[0].size + 0x2000000;
+               gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+                                       + top - gd->bd->bi_dram[1].start;
+       }
+#else
+       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+       gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
+#endif
+#endif
+
+       return 0;
+}
+
 size_t rockchip_sdram_size(phys_addr_t reg)
 {
        u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
index 457b110cd52c1faf8ccde74934a0208f1bcb0e05..6d934f88058a90721f450b3feeb79af850d27e31 100644 (file)
@@ -59,11 +59,3 @@ int dram_init(void)
 
        return 0;
 }
-
-int dram_init_banksize(void)
-{
-       gd->bd->bi_dram[0].start = 0x60000000;
-       gd->bd->bi_dram[0].size = 0x8000000;
-
-       return 0;
-}