mpc5xxx: Add MVBC_P board support
authorAndre Schwarz <andre.schwarz@matrix-vision.de>
Wed, 9 Jul 2008 16:30:44 +0000 (18:30 +0200)
committerGrant Likely <grant.likely@secretlab.ca>
Tue, 15 Jul 2008 16:12:58 +0000 (10:12 -0600)
The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
14 files changed:
CREDITS
MAINTAINERS
MAKEALL
Makefile
board/matrix_vision/mvbc_p/Makefile [new file with mode: 0644]
board/matrix_vision/mvbc_p/config.mk [new file with mode: 0644]
board/matrix_vision/mvbc_p/fpga.c [new file with mode: 0644]
board/matrix_vision/mvbc_p/fpga.h [new file with mode: 0644]
board/matrix_vision/mvbc_p/mvbc_p.c [new file with mode: 0644]
board/matrix_vision/mvbc_p/mvbc_p.h [new file with mode: 0644]
board/matrix_vision/mvbc_p/mvbc_p_autoscript [new file with mode: 0644]
doc/README.mvbc_p [new file with mode: 0644]
include/configs/MVBC_P.h [new file with mode: 0644]
include/mpc5xxx.h

diff --git a/CREDITS b/CREDITS
index 3b6e57dee1d0c929fe9af6d5d5168ee98adcdcae..2b0dab7609b8069ccad97794a667f5a406d4f7cf 100644 (file)
--- a/CREDITS
+++ b/CREDITS
@@ -426,7 +426,7 @@ D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots mor
 
 N: Andre Schwarz
 E: andre.schwarz@matrix-vision.de
-D: Support for Matrix Vision boards (MVBLM7)
+D: Support for Matrix Vision boards (MVBLM7/MVBC_P)
 
 N: Robert Schwebel
 E: r.schwebel@pengutronix.de
index 1f29abb3c71ee17125d56a31c54a431efe2a6dc7..cbe5c47f53193176ce7d11ab406e916864f859e0 100644 (file)
@@ -372,6 +372,7 @@ Peter De Schrijver <p2@mind.be>
 
 Andre Schwarz <andre.schwarz@matrix-vision.de>
 
+       mvbc_p          MPC5200
        mvblm7          MPC8343
 
 Timur Tabi <timur@freescale.com>
diff --git a/MAKEALL b/MAKEALL
index 804dd8876e8c5c8b4010a03b6b537be5c114f0f2..c1a9c6067d583cb944a35add3b981e809ccec62b 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -48,6 +48,7 @@ LIST_5xxx="           \
        mecp5200        \
        motionpro       \
        munices         \
+       MVBC_P          \
        o2dnt           \
        pf5200          \
        PM520           \
index e557d0d36c015994895f4605519b868419d67339..4c7bfb01d6268932748ce11a7e8e492f15793c70 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -745,6 +745,13 @@ uc101_config:              unconfig
 motionpro_config:      unconfig
        @$(MKCONFIG) motionpro ppc mpc5xxx motionpro
 
+MVBC_P_config: unconfig 
+       @mkdir -p $(obj)include
+       @mkdir -p $(obj)board/mvbc_p
+       @ >$(obj)include/config.h
+       @[ -z "$(findstring MVBC_P,$@)" ] || \
+       {       echo "#define CONFIG_MVBC_P"    >>$(obj)include/config.h; }
+       @$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p matrix_vision
 
 #########################################################################
 ## MPC512x Systems
diff --git a/board/matrix_vision/mvbc_p/Makefile b/board/matrix_vision/mvbc_p/Makefile
new file mode 100644 (file)
index 0000000..ea72f77
--- /dev/null
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004-2008
+# Matrix-Vision GmbH, info@matrix-vision.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS  := $(BOARD).o fpga.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+               $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/matrix_vision/mvbc_p/config.mk b/board/matrix_vision/mvbc_p/config.mk
new file mode 100644 (file)
index 0000000..c2c09f4
--- /dev/null
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFF800000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/matrix_vision/mvbc_p/fpga.c b/board/matrix_vision/mvbc_p/fpga.c
new file mode 100644 (file)
index 0000000..356af1a
--- /dev/null
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include "fpga.h"
+#include "mvbc_p.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...)       printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+       fpga_null_fn,
+       fpga_config_fn,
+       fpga_status_fn,
+       fpga_done_fn,
+       fpga_wr_fn,
+       fpga_null_fn,
+       fpga_null_fn,
+       0
+};
+
+Altera_desc cyclone2 = {
+       Altera_CYC2,
+       passive_serial,
+       Altera_EP2C8_SIZE,
+       (void *) &altera_fns,
+       NULL,
+       0
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvbc_p_init_fpga(void)
+{
+       fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n",
+               gd->reloc_off);
+       fpga_init(gd->reloc_off);
+       fpga_add(fpga_altera, &cyclone2);
+       fpga_config_fn(0, 1, 0);
+       udelay(60);
+
+       return 1;
+}
+
+int fpga_null_fn(int cookie)
+{
+       return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+       struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+       u32 dvo = gpio->simple_dvo;
+
+       fpga_debug("SET config : %s\n", assert ? "low" : "high");
+       if (assert)
+               dvo |= FPGA_CONFIG;
+       else
+               dvo &= ~FPGA_CONFIG;
+
+       if (flush)
+               gpio->simple_dvo = dvo;
+
+       return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+       struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+       int result = 0;
+
+       udelay(10);
+       fpga_debug("CONF_DONE check ... ");
+       if (gpio->simple_ival & FPGA_CONF_DONE) {
+               fpga_debug("high\n");
+               result = 1;
+       } else
+               fpga_debug("low\n");
+
+       return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+       struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+       int result = 0;
+
+       fpga_debug("STATUS check ... ");
+       if (gpio->sint_ival & FPGA_STATUS) {
+               fpga_debug("high\n");
+               result = 1;
+       } else
+               fpga_debug("low\n");
+
+       return result;
+}
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+       struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+       u32 dvo = gpio->simple_dvo;
+
+       fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
+       if (assert_clk)
+               dvo |= FPGA_CCLK;
+       else
+               dvo &= ~FPGA_CCLK;
+
+       if (flush)
+               gpio->simple_dvo = dvo;
+
+       return assert_clk;
+}
+
+static inline int _write_fpga(u8 val)
+{
+       int i;
+       struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+       u32 dvo = gpio->simple_dvo;
+
+       for (i=0; i<8; i++) {
+               dvo &= ~FPGA_CCLK;
+               gpio->simple_dvo = dvo;
+               dvo &= ~FPGA_DIN;
+               if (val & 1)
+                       dvo |= FPGA_DIN;
+               gpio->simple_dvo = dvo;
+               dvo |= FPGA_CCLK;
+               gpio->simple_dvo = dvo;
+               val >>= 1;
+       }
+
+       return 0;
+}
+
+int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+{
+       unsigned char *data = (unsigned char *) buf;
+       int i;
+
+       fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+       for (i = 0; i < len; i++)
+               _write_fpga(data[i]);
+       fpga_debug("\n");
+
+       return FPGA_SUCCESS;
+}
diff --git a/board/matrix_vision/mvbc_p/fpga.h b/board/matrix_vision/mvbc_p/fpga.h
new file mode 100644 (file)
index 0000000..3723073
--- /dev/null
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvbc_p_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
diff --git a/board/matrix_vision/mvbc_p/mvbc_p.c b/board/matrix_vision/mvbc_p/mvbc_p.c
new file mode 100644 (file)
index 0000000..b61e84e
--- /dev/null
@@ -0,0 +1,325 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2005-2007
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <malloc.h>
+#include <pci.h>
+#include <i2c.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include "fpga.h"
+#include "mvbc_p.h"
+
+#define SDRAM_MODE     0x00CD0000
+#define SDRAM_CONTROL  0x504F0000
+#define SDRAM_CONFIG1  0xD2322800
+#define SDRAM_CONFIG2  0x8AD70000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_start (int hi_addr)
+{
+       long hi_bit = hi_addr ? 0x01000000 : 0;
+
+       /* unlock mode register */
+       out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit);
+
+       /* precharge all banks */
+       out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
+
+       /* precharge all banks */
+       out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
+
+       /* auto refresh */
+       out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit);
+
+       /* set mode register */
+       out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+       /* normal operation */
+       out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
+}
+
+phys_addr_t initdram (int board_type)
+{
+       ulong dramsize = 0;
+       ulong test1,
+             test2;
+
+       /* setup SDRAM chip selects */
+       out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
+
+       /* setup config registers */
+       out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+       out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+       /* find RAM size using SDRAM CS0 only */
+       sdram_start(0);
+       test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+       sdram_start(1);
+       test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+       if (test1 > test2) {
+               sdram_start(0);
+               dramsize = test1;
+       } else
+               dramsize = test2;
+
+       if (dramsize < (1 << 20))
+               dramsize = 0;
+
+       if (dramsize > 0)
+               out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 +
+                       __builtin_ffs(dramsize >> 20) - 1);
+       else
+               out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0);
+
+       return dramsize;
+}
+
+void mvbc_init_gpio(void)
+{
+       struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+       printf("Ports : 0x%08x\n", gpio->port_config);
+       printf("PORCFG: 0x%08x\n", *(vu_long*)MPC5XXX_CDM_PORCFG);
+
+       out_be32(&gpio->simple_ddr, SIMPLE_DDR);
+       out_be32(&gpio->simple_dvo, SIMPLE_DVO);
+       out_be32(&gpio->simple_ode, SIMPLE_ODE);
+       out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
+
+       out_be32((u32*)&gpio->sint_ode, SINT_ODE);
+       out_be32((u32*)&gpio->sint_ddr, SINT_DDR);
+       out_be32((u32*)&gpio->sint_dvo, SINT_DVO);
+       out_be32((u32*)&gpio->sint_inten, SINT_INTEN);
+       out_be32((u32*)&gpio->sint_itype, SINT_ITYPE);
+       out_be32((u32*)&gpio->sint_gpioe, SINT_GPIOEN);
+
+       out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE);
+       out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR);
+       out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO);
+       out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN);
+
+       printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
+       printf("sint_gpioe  : 0x%08x\n", gpio->sint_gpioe);
+}
+
+void reset_environment(void)
+{
+       char *s, sernr[64];
+
+       printf("\n*** RESET ENVIRONMENT ***\n");
+       memset(sernr, 0, sizeof(sernr));
+       s = getenv("serial#");
+       if (s) {
+               printf("found serial# : %s\n", s);
+               strncpy(sernr, s, 64);
+       }
+       gd->env_valid = 0;
+       env_relocate();
+       if (s)
+               setenv("serial#", sernr);
+}
+
+int misc_init_r(void)
+{
+       char *s = getenv("reset_env");
+
+       if (!s) {
+               if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
+                       return 0;
+               udelay(50000);
+               if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
+                       return 0;
+               udelay(50000);
+               if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
+                       return 0;
+       }
+       printf(" === FACTORY RESET ===\n");
+       reset_environment();
+       saveenv();
+
+       return -1;
+}
+
+int checkboard(void)
+{
+       mvbc_init_gpio();
+       printf("Board: Matrix Vision mvBlueCOUGAR-P\n");
+
+       return 0;
+}
+
+void flash_preinit(void)
+{
+       /*
+        * Now, when we are in RAM, enable flash write
+        * access for detection process.
+        * Note that CS_BOOT cannot be cleared when
+        * executing in flash.
+        */
+       clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1);
+}
+
+void flash_afterinit(ulong size)
+{
+       out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CFG_BOOTCS_START |
+               size));
+       out_be32((u32*)MPC5XXX_CS0_START, START_REG(CFG_BOOTCS_START |
+               size));
+       out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CFG_BOOTCS_START | size,
+               size));
+       out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CFG_BOOTCS_START | size,
+               size));
+}
+
+void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+       unsigned char line = 0xff;
+       u32 base;
+
+       if (PCI_BUS(dev) == 0) {
+               switch (PCI_DEV (dev)) {
+               case 0xa: /* FPGA */
+                       line = 3;
+                       pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
+                       printf("found FPA - enable arbitration\n");
+                       writel(0x03, (u32*)(base + 0x80c0));
+                       writel(0xf0, (u32*)(base + 0x8080));
+                       break;
+               case 0xb: /* LAN */
+                       line = 2;
+                       break;
+               case 0x1a:
+                       break;
+               default:
+                       printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev));
+                       break;
+               }
+               pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
+       }
+}
+
+struct pci_controller hose = {
+       fixup_irq:pci_mvbc_fixup_irq
+};
+
+int mvbc_p_load_fpga(void)
+{
+       size_t data_size = 0;
+       void *fpga_data = NULL;
+       char *datastr = getenv("fpgadata");
+       char *sizestr = getenv("fpgadatasize");
+
+       if (datastr)
+               fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
+       if (sizestr)
+               data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
+
+       return fpga_load(0, fpga_data, data_size);
+}
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+       char *s;
+       int load_fpga = 1;
+
+       mvbc_p_init_fpga();
+       s = getenv("skip_fpga");
+       if (s) {
+               printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
+               load_fpga = 0;
+       }
+       if (load_fpga) {
+               printf("loading FPGA ... ");
+               mvbc_p_load_fpga();
+               printf("done\n");
+       }
+       pci_mpc5xxx_init(&hose);
+}
+
+u8 *dhcp_vendorex_prep(u8 *e)
+{
+       char *ptr;
+
+       /* DHCP vendor-class-identifier = 60 */
+       if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
+               *e++ = 60;
+               *e++ = strlen(ptr);
+               while (*ptr)
+                       *e++ = *ptr++;
+       }
+       /* DHCP_CLIENT_IDENTIFIER = 61 */
+       if ((ptr = getenv("dhcp_client_id"))) {
+               *e++ = 61;
+               *e++ = strlen(ptr);
+               while (*ptr)
+                       *e++ = *ptr++;
+       }
+
+       return e;
+}
+
+u8 *dhcp_vendorex_proc (u8 *popt)
+{
+       return NULL;
+}
+
+void show_boot_progress(int val)
+{
+       struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+       switch(val) {
+       case 0: /* FPGA ok */
+               setbits_be32(&gpio->simple_dvo, 0x80);
+               break;
+       case 1:
+               setbits_be32(&gpio->simple_dvo, 0x40);
+               break;
+       case 12:
+               setbits_be32(&gpio->simple_dvo, 0x20);
+               break;
+       case 15:
+               setbits_be32(&gpio->simple_dvo, 0x10);
+               break;
+       default:
+               break;
+       }
+
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+       ft_cpu_setup(blob, bd);
+       fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}
diff --git a/board/matrix_vision/mvbc_p/mvbc_p.h b/board/matrix_vision/mvbc_p/mvbc_p.h
new file mode 100644 (file)
index 0000000..3330798
--- /dev/null
@@ -0,0 +1,43 @@
+#ifndef __MVBC_H__
+#define __MVBC_H__
+
+#define LED_G0          MPC5XXX_GPIO_SIMPLE_PSC2_0
+#define LED_G1          MPC5XXX_GPIO_SIMPLE_PSC2_1
+#define LED_Y           MPC5XXX_GPIO_SIMPLE_PSC2_2
+#define LED_R           MPC5XXX_GPIO_SIMPLE_PSC2_3
+#define ARB_X_EN        MPC5XXX_GPIO_WKUP_PSC2_4
+
+#define FPGA_DIN        MPC5XXX_GPIO_SIMPLE_PSC3_0
+#define FPGA_CCLK       MPC5XXX_GPIO_SIMPLE_PSC3_1
+#define FPGA_CONF_DONE  MPC5XXX_GPIO_SIMPLE_PSC3_2
+#define FPGA_CONFIG     MPC5XXX_GPIO_SIMPLE_PSC3_3
+#define FPGA_STATUS     MPC5XXX_GPIO_SINT_PSC3_4
+
+#define MAN_RST         MPC5XXX_GPIO_WKUP_PSC6_0
+#define WD_TS           MPC5XXX_GPIO_WKUP_PSC6_1
+#define WD_WDI          MPC5XXX_GPIO_SIMPLE_PSC6_2
+#define COP_PRESENT     MPC5XXX_GPIO_SIMPLE_PSC6_3
+#define FACT_RST        MPC5XXX_GPIO_WKUP_6
+#define FLASH_RBY       MPC5XXX_GPIO_WKUP_7
+
+#define SIMPLE_DDR      (LED_G0 | LED_G1 | LED_Y | LED_R | \
+                        FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI)
+#define SIMPLE_DVO      (FPGA_CONFIG)
+#define SIMPLE_ODE      (FPGA_CONFIG)
+#define SIMPLE_GPIOEN   (LED_G0 | LED_G1 | LED_Y | LED_R | \
+                        FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\
+                        WD_WDI | COP_PRESENT)
+
+#define SINT_ODE        0
+#define SINT_DDR        0
+#define SINT_DVO        0
+#define SINT_INTEN      0
+#define SINT_ITYPE      0
+#define SINT_GPIOEN     (FPGA_STATUS)
+
+#define WKUP_ODE        (MAN_RST)
+#define WKUP_DIR        (ARB_X_EN|MAN_RST|WD_TS)
+#define WKUP_DO         (ARB_X_EN|MAN_RST|WD_TS)
+#define WKUP_EN         (ARB_X_EN|MAN_RST|WD_TS|FACT_RST|FLASH_RBY)
+
+#endif
diff --git a/board/matrix_vision/mvbc_p/mvbc_p_autoscript b/board/matrix_vision/mvbc_p/mvbc_p_autoscript
new file mode 100644 (file)
index 0000000..5cee6c5
--- /dev/null
@@ -0,0 +1,44 @@
+echo
+echo "==== running autoscript ===="
+echo
+setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
+setenv ramkernel setenv kernel_boot \${loadaddr}
+setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
+setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
+setenv bootfromflash run flashkernel cpird ramparam addcons e1000para bootdtb
+setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
+setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
+setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
+setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
+if test ${console} = yes;
+then
+setenv addcons setenv bootargs \${bootargs} console=ttyPSC\${console_nr},\${baudrate}N8
+else
+setenv addcons setenv bootargs \${bootargs} console=tty0
+fi
+setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=1500 e1000.SmartPowerDownEnable=1
+setenv set_static_ip setenv ipaddr \${static_ipaddr}
+setenv set_static_nm setenv netmask \${static_netmask}
+setenv set_static_gw setenv gatewayip \${static_gateway}
+setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
+setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
+if test ${autoscr_boot} != no;
+then
+  if test ${netboot} = yes;
+  then
+    bootp
+    if test $? = 0;
+    then
+      echo "=== bootp succeeded -> netboot ==="
+      run set_ip
+      run getdtb rundtb bootfromnet ramparam addcons e1000para bootdtb
+    else
+      echo "=== netboot failed ==="
+    fi
+  fi
+  run set_static_ip set_static_nm set_static_gw set_ip
+  echo "=== bootfromflash ==="
+  run cpdtb rundtb bootfromflash
+else
+  echo "=== boot stopped with autoscr_boot no ==="
+fi
diff --git a/doc/README.mvbc_p b/doc/README.mvbc_p
new file mode 100644 (file)
index 0000000..d32e57f
--- /dev/null
@@ -0,0 +1,74 @@
+Matrix Vision mvBlueCOUGAR-P (mvBC-P)
+-------------------------------------
+
+1.     Board Description
+
+       The mvBC-P is a 70x40x40mm multi board gigabit ethernet network camera
+       with main focus on GigEVision protocol in combination with local image
+       preprocessing.
+
+       Power Supply is either VDC 48V or Pover over Ethernet (PoE).
+
+2      System Components
+
+2.1    CPU     
+       Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
+       64MB SDRAM @ 133MHz.
+       8 MByte Nor Flash on local bus.
+       1 serial ports. Console running on ttyS0 @ 115200 8N1.
+
+2.2    PCI
+       PCI clock fixed at 66MHz. Arbitration inside FPGA.
+       Intel GD82541ER network MAC/PHY and FPGA connected.
+       
+2.3    FPGA
+       Altera Cyclone-II EP2C8 with PCI DMA engine.
+       Connects to Matrix Vision specific CCD/CMOS sensor interface.
+       Utilizes 64MB Nand Flash.
+
+2.3.1  I/O @ FPGA
+       2 Outputs : photo coupler
+       2 Inputs  : photo coupler
+
+2.4    I2C
+       LM75 @ 0x90 for temperature monitoring.
+       EEPROM @ 0xA0 for vendor specifics.
+       image sensor interface (slave adresses depend on sensor)
+
+3      Flash layout.
+
+       reset vector is 0x00000100, i.e. "LOWBOOT".
+
+       FF800000        u-boot
+       FF840000        u-boot script image
+       FF850000        redundant u-boot script image
+       FF860000        FPGA raw bit file
+       FF8A0000        tbd.
+       FF900000        root FS
+       FFC00000        kernel
+       FFFC0000        device tree blob
+       FFFD0000        redundant device tree blob
+       FFFE0000        environment
+       FFFF0000        redundant environment
+
+       mtd partitions are propagated to linux kernel via device tree blob.
+
+4      Booting
+
+       On startup the bootscript @ FF840000 is executed. This script can be
+       exchanged easily. Default boot mode is "boot from flash", i.e. system
+       works stand-alone.
+
+       This behaviour depends on some environment variables :
+
+       "netboot" : yes ->try dhcp/bootp and boot from network.
+       A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
+       DHCP server configuration, e.g. to provide different images to
+       different devices.
+
+       During netboot the system tries to get 3 image files:
+       1. Kernel - name + data is given during BOOTP.
+       2. Initrd - name is stored in "initrd_name"
+       3. device tree blob - name is stored in "dtb_name"
+       Fallback files are the flash versions.
+
diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h
new file mode 100644 (file)
index 0000000..04580b7
--- /dev/null
@@ -0,0 +1,316 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2008
+ * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <version.h>
+
+#define CONFIG_MPC5xxx 1
+#define CONFIG_MPC5200         1
+
+#define CFG_MPC5XXX_CLKIN      33000000
+
+#define BOOTFLAG_COLD          0x01
+#define BOOTFLAG_WARM          0x02
+
+#define CONFIG_MISC_INIT_R     1
+
+#define CFG_CACHELINE_SIZE     32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT    5
+#endif
+
+#define CONFIG_PSC_CONSOLE     1
+#define CONFIG_BAUDRATE                115200
+#define CFG_BAUDRATE_TABLE     {9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CONFIG_PCI             1
+#define CONFIG_PCI_PNP         1
+#undef CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE        1
+
+#define CONFIG_PCI_MEM_BUS     0x40000000
+#define CONFIG_PCI_MEM_PHYS    CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE    0x10000000
+
+#define CONFIG_PCI_IO_BUS      0x50000000
+#define CONFIG_PCI_IO_PHYS     CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE     0x01000000
+
+#define CFG_XLB_PIPELINING     1
+#define CONFIG_HIGH_BATS       1
+
+#define MV_CI                  mvBlueCOUGAR-P
+#define MV_VCI                 mvBlueCOUGAR-P
+#define MV_FPGA_DATA           0xff860000
+#define MV_FPGA_SIZE           0x0003c886
+#define MV_KERNEL_ADDR         0xffc00000
+#define MV_INITRD_ADDR         0xff900000
+#define MV_INITRD_LENGTH       0x00300000
+#define MV_SCRATCH_ADDR                0x00000000
+#define MV_SCRATCH_LENGTH      MV_INITRD_LENGTH
+#define MV_AUTOSCR_ADDR                0xff840000
+#define MV_AUTOSCR_ADDR2       0xff850000
+#define MV_DTB_ADDR            0xfffc0000
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
+#define MV_KERNEL_ADDR_RAM     0x00100000
+#define MV_DTB_ADDR_RAM                0x00600000
+#define MV_INITRD_ADDR_RAM     0x01000000
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT       1
+#define CONFIG_OF_BOARD_SETUP  1
+
+#define OF_CPU                 "PowerPC,5200@0"
+#define OF_SOC                 "soc5200@f0000000"
+#define OF_TBCLK               (bd->bi_busfreq / 4)
+#define MV_DTB_NAME            mvbc-p.dtb
+#define CONFIG_OF_STDOUT_VIA_ALIAS     1
+
+/*
+ * Supported commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_FPGA
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_BOOTP_VENDOREX
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_RANDOM_DELAY
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+/*
+ * Autoboot
+ */
+#define CONFIG_BOOTDELAY               2
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR       "s"
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_RESET_TO_RETRY          1000
+
+#define CONFIG_BOOTCOMMAND     "if imi ${autoscr_addr}; \
+                                       then autoscr ${autoscr_addr};   \
+                                       else autoscr ${autoscr_addr2};  \
+                               fi;"
+
+#define CONFIG_BOOTARGS                "root=/dev/ram ro rootfstype=squashfs"
+#define CONFIG_ENV_OVERWRITE
+
+#define XMK_STR(x)      #x
+#define MK_STR(x)       XMK_STR(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS                              \
+       "console_nr=0\0"                                        \
+       "console=yes\0"                                         \
+       "stdin=serial\0"                                        \
+       "stdout=serial\0"                                       \
+       "stderr=serial\0"                                       \
+       "fpga=0\0"                                              \
+       "fpgadata=" MK_STR(MV_FPGA_DATA) "\0"                   \
+       "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"               \
+       "autoscr_addr=" MK_STR(MV_AUTOSCR_ADDR) "\0"            \
+       "autoscr_addr2=" MK_STR(MV_AUTOSCR_ADDR2) "\0"          \
+       "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0"           \
+       "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"   \
+       "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0"           \
+       "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"   \
+       "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0"       \
+       "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0"                 \
+       "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0"         \
+       "dtb_name=" MK_STR(MV_DTB_NAME) "\0"                    \
+       "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0"         \
+       "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0"     \
+       "mv_version=" U_BOOT_VERSION "\0"                       \
+       "dhcp_client_id=" MK_STR(MV_CI) "\0"                    \
+       "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0"     \
+       "netretry=no\0"                                         \
+       "use_static_ipaddr=no\0"                                \
+       "static_ipaddr=192.168.90.10\0"                         \
+       "static_netmask=255.255.255.0\0"                        \
+       "static_gateway=0.0.0.0\0"                              \
+       "initrd_name=uInitrd.mvbc-p-rfs\0"                      \
+       "zcip=no\0"                                             \
+       "netboot=yes\0"                                         \
+       "mvtest=Ff\0"                                           \
+       "tried_bootfromflash=no\0"                              \
+       "tried_bootfromnet=no\0"                                \
+       "use_dhcp=yes\0"                                        \
+       "gev_start=yes\0"                                       \
+       "mvbcdma_debug=0\0"                                     \
+       "mvbcia_debug=0\0"                                      \
+       "propdev_debug=0\0"                                     \
+       "gevss_debug=0\0"                                       \
+       "watchdog=1\0"                                          \
+       ""
+
+#undef XMK_STR
+#undef MK_STR
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBCLK_EQUALS_XLBCLK
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2
+
+/*
+ * Flash configuration
+ */
+#undef         CONFIG_FLASH_16BIT
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI_AMD_RESET 1
+#define CFG_FLASH_EMPTY_INFO
+
+#define CFG_FLASH_ERASE_TOUT   50000
+#define CFG_FLASH_WRITE_TOUT   1000
+
+#define CFG_MAX_FLASH_BANKS    1
+#define CFG_MAX_FLASH_SECT     256
+
+#define CFG_LOWBOOT
+#define CFG_FLASH_BASE         TEXT_BASE
+#define CFG_FLASH_SIZE         0x00800000
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH
+#undef CFG_FLASH_PROTECTION
+
+#define CFG_ENV_ADDR           0xFFFE0000
+#define CFG_ENV_SIZE           0x10000
+#define CFG_ENV_SECT_SIZE      0x10000
+#define CFG_ENV_ADDR_REDUND    (CFG_ENV_ADDR+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND    CFG_ENV_SIZE
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR               0xF0000000
+#define CFG_SDRAM_BASE         0x00000000
+#define CFG_DEFAULT_MBAR       0x80000000
+
+#define CFG_INIT_RAM_ADDR      MPC5XXX_SRAM
+#define CFG_INIT_RAM_END       MPC5XXX_SRAM_SIZE
+
+#define CFG_GBL_DATA_SIZE      128
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE       TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT            1
+#endif
+
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
+#define CFG_MONITOR_LEN                (512 << 10)
+#define CFG_MALLOC_LEN         (512 << 10)
+#define CFG_BOOTMAPSZ          (8 << 20)
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_NET_RETRY_COUNT 5
+
+#define CONFIG_E1000
+#define CONFIG_E1000_FALLBACK_MAC      0xb6b445ebfbc0
+#undef CONFIG_MPC5xxx_FEC
+#undef CONFIG_PHY_ADDR
+#define CONFIG_NETDEV          eth0
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CFG_PROMPT_HUSH_PS2    "> "
+#undef         CFG_LONGHELP
+#define CFG_PROMPT             "=> "
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE             1024
+#else
+#define CFG_CBSIZE             256
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS            16
+#define CFG_BARGSIZE           CFG_CBSIZE
+
+#define CFG_MEMTEST_START      0x00800000
+#define CFG_MEMTEST_END                0x02f00000
+
+#define CFG_HZ                 1000
+
+/* default load address */
+#define CFG_LOAD_ADDR          0x02000000
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR        0x00200000
+
+/*
+ * Various low-level settings
+ */
+#define CFG_GPS_PORT_CONFIG    0x20000004
+
+#define CFG_HID0_INIT          (HID0_ICE | HID0_ICFI)
+#define CFG_HID0_FINAL         HID0_ICE
+
+#define CFG_BOOTCS_START       CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE                CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG         0x00047800
+#define CFG_CS0_START          CFG_FLASH_BASE
+#define CFG_CS0_SIZE           CFG_FLASH_SIZE
+
+#define CFG_CS_BURST           0x000000f0
+#define CFG_CS_DEADCYCLE       0x33333303
+
+#define CFG_RESET_ADDRESS      0x00000100
+
+#undef FPGA_DEBUG
+#undef CFG_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA            CFG_ALTERA_CYCLON2
+#define CONFIG_FPGA_ALTERA     1
+#define CONFIG_FPGA_CYCLON2    1
+#define CONFIG_FPGA_COUNT      1
+
+#endif
index a4581a3e6bb818cd506c31d8c1c2d53de43e8a8d..5d11ef0f48054208456b6e51842d4498383654b6 100644 (file)
 #define GPIO_PSC3_9            0x04000000UL
 #define GPIO_PSC1_4            0x01000000UL
 
+#define MPC5XXX_GPIO_SIMPLE_PSC6_3   0x20000000UL
+#define MPC5XXX_GPIO_SIMPLE_PSC6_2   0x10000000UL
+#define MPC5XXX_GPIO_SIMPLE_PSC3_7   0x00002000UL
+#define MPC5XXX_GPIO_SIMPLE_PSC3_6   0x00001000UL
+#define MPC5XXX_GPIO_SIMPLE_PSC3_3   0x00000800UL
+#define MPC5XXX_GPIO_SIMPLE_PSC3_2   0x00000400UL
+#define MPC5XXX_GPIO_SIMPLE_PSC3_1   0x00000200UL
+#define MPC5XXX_GPIO_SIMPLE_PSC3_0   0x00000100UL
+#define MPC5XXX_GPIO_SIMPLE_PSC2_3   0x00000080UL
+#define MPC5XXX_GPIO_SIMPLE_PSC2_2   0x00000040UL
+#define MPC5XXX_GPIO_SIMPLE_PSC2_1   0x00000020UL
+#define MPC5XXX_GPIO_SIMPLE_PSC2_0   0x00000010UL
+#define MPC5XXX_GPIO_SIMPLE_PSC1_3   0x00000008UL
+#define MPC5XXX_GPIO_SIMPLE_PSC1_2   0x00000004UL
+#define MPC5XXX_GPIO_SIMPLE_PSC1_1   0x00000002UL
+#define MPC5XXX_GPIO_SIMPLE_PSC1_0   0x00000001UL
+
+#define MPC5XXX_GPIO_SINT_PSC3_5     0x02
+#define MPC5XXX_GPIO_SINT_PSC3_4     0x01
+
+#define MPC5XXX_GPIO_WKUP_7          0x80
+#define MPC5XXX_GPIO_WKUP_6          0x40
+#define MPC5XXX_GPIO_WKUP_PSC6_1     0x20
+#define MPC5XXX_GPIO_WKUP_PSC6_0     0x10
+#define MPC5XXX_GPIO_WKUP_ETH17      0x08
+#define MPC5XXX_GPIO_WKUP_PSC3_9     0x04
+#define MPC5XXX_GPIO_WKUP_PSC2_4     0x02
+#define MPC5XXX_GPIO_WKUP_PSC1_4     0x01
+
 /* PCI registers */
 #define MPC5XXX_PCI_CMD                (MPC5XXX_PCI + 0x04)
 #define MPC5XXX_PCI_CFG                (MPC5XXX_PCI + 0x0c)