phy: add support for backplane kr mode

Add generic support for backplane kr modes currently available:
10gbase-kr, 40gbase-kr4. Remove platform generic fixups
(armv8/layerscape and powerpc) for ethernet interfaces specified
in device tree as supported backplane modes.

Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 87c3e05f4585ac44ee2f9601bd930cb83926d0b3..077438765c8861eef834d6fbbc079436b1035b1c 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #include <common.h>
@@ -31,6 +32,14 @@
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
+       const char *conn;
+
+       /* Do NOT apply fixup for backplane modes specified in DT */
+       if (phyc == PHY_INTERFACE_MODE_XGMII) {
+               conn = fdt_getprop(blob, offset, "phy-connection-type", NULL);
+               if (is_backplane_mode(conn))
+                       return 0;
+       }
        return fdt_setprop_string(blob, offset, "phy-connection-type",
                                         phy_string_for_interface(phyc));
 }

diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 485c2d4feb0eefd4f3e9a5c682be2013a86e66b5..67f8b1000183c104ba85c1b2684fd9c0ee408e69 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2009-2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  *
  * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
  * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
@@ -76,6 +77,14 @@ void ft_fixup_num_cores(void *blob) {
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
+       const char *conn;
+
+       /* Do NOT apply fixup for backplane modes specified in DT */
+       if (phyc == PHY_INTERFACE_MODE_XGMII) {
+               conn = fdt_getprop(blob, offset, "phy-connection-type", NULL);
+               if (is_backplane_mode(conn))
+                       return 0;
+       }
        return fdt_setprop_string(blob, offset, "phy-connection-type",
                                         phy_string_for_interface(phyc));
 }

diff --git a/include/phy_interface.h b/include/phy_interface.h
index 31ca72a81fd152ea2cfeef43b8c91a6af67bf920..882e4af8ffd55dbad6390902662e71c530f20cef 100644 (file)
--- a/include/phy_interface.h
+++ b/include/phy_interface.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  *     Andy Fleming <afleming@gmail.com>
  *
  * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
@@ -67,6 +68,15 @@ static const char * const phy_interface_strings[] = {
        [PHY_INTERFACE_MODE_NONE]               = "",
 };
 
+/* Backplane modes:
+ * are considered a sub-type of phy_interface_t: XGMII
+ * and are specified in "phy-connection-type" with one of the following strings
+ */
+static const char * const backplane_mode_strings[] = {
+       "10gbase-kr",
+       "40gbase-kr4",
+};
+
 static inline const char *phy_string_for_interface(phy_interface_t i)
 {
        /* Default to unknown */
@@ -76,4 +86,17 @@ static inline const char *phy_string_for_interface(phy_interface_t i)
        return phy_interface_strings[i];
 }
 
+static inline bool is_backplane_mode(const char *phyconn)
+{
+       int i;
+
+       if (!phyconn)
+               return false;
+       for (i = 0; i < ARRAY_SIZE(backplane_mode_strings); i++) {
+               if (!strcmp(phyconn, backplane_mode_strings[i]))
+                       return true;
+       }
+       return false;
+}
+
 #endif /* _PHY_INTERFACE_H */