| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| BR_PS_8 /* 8 bit Port */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
/* 0xF0000801 */
-#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
| OR_GPCM_CSNT \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
/* 0xFA000801 */
-#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| BR_PS_8 /* 8 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
| OR_GPCM_CSNT \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
/* 0xFA000801 */
-#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| BR_PS_8 /* 8 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
| OR_GPCM_CSNT \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB \
| OR_GPCM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB \
| OR_GPCM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| BR_MS_GPCM \
| BR_V)
/* 0xF8008801 */
-#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \
| OR_GPCM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_XACS \
| BR_MS_GPCM \
| BR_V)
/* 0xF8010801 */
-#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
| OR_GPCM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_XACS \
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| BR_PS_16 \
| BR_MS_GPCM \
| BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \
| OR_GPCM_XACS \
| OR_GPCM_SCY_9 \
| OR_GPCM_EHTR_SET \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_4MB \
| OR_GPCM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
BR_MS_GPCM |\
BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB |\
OR_GPCM_SCY_10 |\
OR_GPCM_EHTR |\
OR_GPCM_TRLX |\
#define NAND_CACHE_PAGES 64
#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\
- (2<<BR_DECC_SHIFT) |\
+ BR_DECC_CHK_GEN |\
BR_PS_8 |\
BR_MS_FCM |\
BR_V)
-#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB |\
OR_FCM_PGS |\
OR_FCM_CSCT |\
OR_FCM_CST |\
BR_MS_GPCM |\
BR_V)
-#define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_7 | OR_GPCM_TRLX_SET)
/*
* CPLD setup
BR_MS_GPCM |\
BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xFFFF8814
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_SCY_1 | OR_GPCM_TRLX_SET)
/*
* HW-Watchdog
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_5 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_PS_8 | /* 8 bit port size */ \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_BR3_PRELIM (\
CONFIG_SYS_PAXE_BASE | \
- (1 << BR_PS_SHIFT) | \
+ BR_PS_8 | \
BR_V)
#define CONFIG_SYS_OR3_PRELIM (\
- MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
+ OR_AM_256MB | \
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
#define CONFIG_SYS_BR4_PRELIM (\
CONFIG_SYS_BFTIC3_BASE |\
- (1 << BR_PS_SHIFT) | \
+ BR_PS_8 | \
BR_V)
#define CONFIG_SYS_OR4_PRELIM (\
- MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
+ OR_AM_256MB|\
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV2 |\
OR_GPCM_SCY_2 |\
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_5 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_PS_8 | /* 8 bit port size */ \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_BR3_PRELIM (\
CONFIG_SYS_PAXE_BASE | \
- (1 << BR_PS_SHIFT) | \
+ BR_PS_8 | \
BR_V)
#define CONFIG_SYS_OR3_PRELIM (\
- MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
+ OR_AM_256MB | \
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_5 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_PS_8 | /* 8 bit port size */ \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_MS_GPCM | \
BR_V)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV4 | \
OR_GPCM_SCY_2 | \
BR_PS_16 | \
BR_MS_GPCM | \
BR_V)
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \
OR_GPCM_SCY_4 | \
OR_GPCM_TRLX_CLEAR | \
OR_GPCM_EHTR_CLEAR)
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_5 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_PS_8 | /* 8 bit port size */ \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_MS_GPCM | \
BR_V)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV4 | \
OR_GPCM_SCY_2 | \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_5 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_PS_8 | /* 8 bit port size */ \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_MS_GPCM | \
BR_V)
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \
OR_GPCM_SCY_5 | \
OR_GPCM_TRLX_CLEAR | \
OR_GPCM_EHTR_CLEAR)
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_5 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_PS_8 | /* 8 bit port size */ \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_MS_GPCM | \
BR_V)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV4 | \
OR_GPCM_SCY_2 | \
BR_PS_16 | \
BR_MS_GPCM | \
BR_V)
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \
OR_GPCM_SCY_4 | \
OR_GPCM_TRLX_CLEAR | \
OR_GPCM_EHTR_CLEAR)
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_5 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_PS_8 | /* 8 bit port size */ \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_PS_16 | \
BR_MS_UPMA | \
BR_V)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB)
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
BR_PS_16 | \
BR_V)
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV4 | \
OR_GPCM_SCY_3 | \
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \
| OR_GPCM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
* 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
*/
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
| OR_SDRAM_XAM \
| ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
| ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_SCY_5 \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_5 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_PS_8 | /* 8 bit port size */ \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_PS_16 | \
BR_MS_UPMA | \
BR_V)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB)
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
BR_PS_16 | \
BR_V)
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV4 | \
OR_GPCM_SCY_3 | \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_5 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_PS_8 | /* 8 bit port size */ \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_MS_GPCM | \
BR_V)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV4 | \
OR_GPCM_SCY_2 | \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_5 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_PS_8 | /* 8 bit port size */ \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
BR_MS_GPCM | \
BR_V)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV4 | \
OR_GPCM_SCY_2 | \
BR_MS_GPCM | \
BR_V)
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB \
| OR_GPCM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \