arm: ls1021atwr: Enable RGMII TX/RX clock internal delay for AR8033
authorAlison Wang <b18965@freescale.com>
Tue, 11 Apr 2017 07:02:13 +0000 (15:02 +0800)
committerYork Sun <york.sun@nxp.com>
Mon, 24 Apr 2017 15:59:43 +0000 (08:59 -0700)
Since commit ce412b7, RGMII TX clock internal delay is not enabled
for AR8033 unconditionally. On LS1021ATWR board, the third port
eTSEC3 uses AR8033 in RGMII mode. The TX/RX internal delay needs to
be enabled.

This patch will set PHY_INTERFACE_MODE_RGMII_ID to enable RGMII TX/RX
clock internal delay for AR8033 on the third port.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
board/freescale/ls1021atwr/ls1021atwr.c

index d96fd774d36b3d7e5c8950fa298e053f1c8780df..ff32d5cb28ea1c7c1410b9b46a265a2a47dab40e 100644 (file)
@@ -273,6 +273,7 @@ int board_eth_init(bd_t *bis)
 #endif
 #ifdef CONFIG_TSEC3
        SET_STD_TSEC_INFO(tsec_info[num], 3);
+       tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
        num++;
 #endif
        if (!num) {