--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _ASM_ARCH_SDRAM_H
+#define _ASM_ARCH_SDRAM_H
+
+enum {
+ DDR4 = 0,
+ DDR3 = 0x3,
+ LPDDR2 = 0x5,
+ LPDDR3 = 0x6,
+ LPDDR4 = 0x7,
+ UNUSED = 0xFF
+};
+
+struct sdram_cap_info {
+ unsigned int rank;
+ /* dram column number, 0 means this channel is invalid */
+ unsigned int col;
+ /* dram bank number, 3:8bank, 2:4bank */
+ unsigned int bk;
+ /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
+ unsigned int bw;
+ /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
+ unsigned int dbw;
+ /*
+ * row_3_4 = 1: 6Gb or 12Gb die
+ * row_3_4 = 0: normal die, power of 2
+ */
+ unsigned int row_3_4;
+ unsigned int cs0_row;
+ unsigned int cs1_row;
+ unsigned int ddrconfig;
+};
+
+struct sdram_base_params {
+ unsigned int ddr_freq;
+ unsigned int dramtype;
+ unsigned int num_channels;
+ unsigned int stride;
+ unsigned int odt;
+};
+
+/*
+ * sys_reg bitfield struct
+ * [31] row_3_4_ch1
+ * [30] row_3_4_ch0
+ * [29:28] chinfo
+ * [27] rank_ch1
+ * [26:25] col_ch1
+ * [24] bk_ch1
+ * [23:22] cs0_row_ch1
+ * [21:20] cs1_row_ch1
+ * [19:18] bw_ch1
+ * [17:16] dbw_ch1;
+ * [15:13] ddrtype
+ * [12] channelnum
+ * [11] rank_ch0
+ * [10:9] col_ch0
+ * [8] bk_ch0
+ * [7:6] cs0_row_ch0
+ * [5:4] cs1_row_ch0
+ * [3:2] bw_ch0
+ * [1:0] dbw_ch0
+*/
+#define SYS_REG_DDRTYPE_SHIFT 13
+#define DDR_SYS_REG_VERSION 2
+#define SYS_REG_DDRTYPE_MASK 7
+#define SYS_REG_NUM_CH_SHIFT 12
+#define SYS_REG_NUM_CH_MASK 1
+#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
+#define SYS_REG_ROW_3_4_MASK 1
+#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
+#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
+#define SYS_REG_ENC_CHINFO(ch) (1 << SYS_REG_CHINFO_SHIFT(ch))
+#define SYS_REG_ENC_DDRTYPE(n) ((n) << SYS_REG_DDRTYPE_SHIFT)
+#define SYS_REG_ENC_NUM_CH(n) (((n) - SYS_REG_NUM_CH_MASK) << \
+ SYS_REG_NUM_CH_SHIFT)
+#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
+#define SYS_REG_RANK_MASK 1
+#define SYS_REG_ENC_RANK(n, ch) (((n) - SYS_REG_RANK_MASK) << \
+ SYS_REG_RANK_SHIFT(ch))
+#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
+#define SYS_REG_COL_MASK 3
+#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << SYS_REG_COL_SHIFT(ch))
+#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
+#define SYS_REG_BK_MASK 1
+#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \
+ SYS_REG_BK_SHIFT(ch))
+#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
+#define SYS_REG_CS0_ROW_MASK 3
+#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
+#define SYS_REG_CS1_ROW_MASK 3
+#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
+#define SYS_REG_BW_MASK 3
+#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch))
+#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
+#define SYS_REG_DBW_MASK 3
+#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
+
+#define SYS_REG_ENC_VERSION(n) ((n) << 28)
+#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
+ (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
+ (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+ (5 + 2 * (ch)); \
+ } while (0)
+
+#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \
+ (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \
+ (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \
+ (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \
+ (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+ (4 + 2 * (ch)); \
+ } while (0)
+
+#define SYS_REG_CS1_COL_SHIFT(ch) (0 + 2 * (ch))
+#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch))
+
+/* Get sdram size decode from reg */
+size_t rockchip_sdram_size(phys_addr_t reg);
+
+/* Called by U-Boot board_init_r for Rockchip SoCs */
+int dram_init(void);
+
+#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG)
+inline void sdram_print_dram_type(unsigned char dramtype)
+{
+}
+
+inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+ struct sdram_base_params *base)
+{
+}
+
+inline void sdram_print_stride(unsigned int stride)
+{
+}
+#else
+void sdram_print_dram_type(unsigned char dramtype);
+void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+ struct sdram_base_params *base);
+void sdram_print_stride(unsigned int stride);
+#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
+
+#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
- */
-
-#ifndef _ASM_ARCH_SDRAM_COMMON_H
-#define _ASM_ARCH_SDRAM_COMMON_H
-
-enum {
- DDR4 = 0,
- DDR3 = 0x3,
- LPDDR2 = 0x5,
- LPDDR3 = 0x6,
- LPDDR4 = 0x7,
- UNUSED = 0xFF
-};
-
-struct sdram_cap_info {
- unsigned int rank;
- /* dram column number, 0 means this channel is invalid */
- unsigned int col;
- /* dram bank number, 3:8bank, 2:4bank */
- unsigned int bk;
- /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
- unsigned int bw;
- /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
- unsigned int dbw;
- /*
- * row_3_4 = 1: 6Gb or 12Gb die
- * row_3_4 = 0: normal die, power of 2
- */
- unsigned int row_3_4;
- unsigned int cs0_row;
- unsigned int cs1_row;
- unsigned int ddrconfig;
-};
-
-struct sdram_base_params {
- unsigned int ddr_freq;
- unsigned int dramtype;
- unsigned int num_channels;
- unsigned int stride;
- unsigned int odt;
-};
-
-/*
- * sys_reg bitfield struct
- * [31] row_3_4_ch1
- * [30] row_3_4_ch0
- * [29:28] chinfo
- * [27] rank_ch1
- * [26:25] col_ch1
- * [24] bk_ch1
- * [23:22] cs0_row_ch1
- * [21:20] cs1_row_ch1
- * [19:18] bw_ch1
- * [17:16] dbw_ch1;
- * [15:13] ddrtype
- * [12] channelnum
- * [11] rank_ch0
- * [10:9] col_ch0
- * [8] bk_ch0
- * [7:6] cs0_row_ch0
- * [5:4] cs1_row_ch0
- * [3:2] bw_ch0
- * [1:0] dbw_ch0
-*/
-#define SYS_REG_DDRTYPE_SHIFT 13
-#define DDR_SYS_REG_VERSION 2
-#define SYS_REG_DDRTYPE_MASK 7
-#define SYS_REG_NUM_CH_SHIFT 12
-#define SYS_REG_NUM_CH_MASK 1
-#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
-#define SYS_REG_ROW_3_4_MASK 1
-#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
-#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
-#define SYS_REG_ENC_CHINFO(ch) (1 << SYS_REG_CHINFO_SHIFT(ch))
-#define SYS_REG_ENC_DDRTYPE(n) ((n) << SYS_REG_DDRTYPE_SHIFT)
-#define SYS_REG_ENC_NUM_CH(n) (((n) - SYS_REG_NUM_CH_MASK) << \
- SYS_REG_NUM_CH_SHIFT)
-#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
-#define SYS_REG_RANK_MASK 1
-#define SYS_REG_ENC_RANK(n, ch) (((n) - SYS_REG_RANK_MASK) << \
- SYS_REG_RANK_SHIFT(ch))
-#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
-#define SYS_REG_COL_MASK 3
-#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << SYS_REG_COL_SHIFT(ch))
-#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
-#define SYS_REG_BK_MASK 1
-#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \
- SYS_REG_BK_SHIFT(ch))
-#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
-#define SYS_REG_CS0_ROW_MASK 3
-#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
-#define SYS_REG_CS1_ROW_MASK 3
-#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
-#define SYS_REG_BW_MASK 3
-#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch))
-#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
-#define SYS_REG_DBW_MASK 3
-#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
-
-#define SYS_REG_ENC_VERSION(n) ((n) << 28)
-#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
- (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
- (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
- (5 + 2 * (ch)); \
- } while (0)
-
-#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \
- (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \
- (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \
- (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \
- (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
- (4 + 2 * (ch)); \
- } while (0)
-
-#define SYS_REG_CS1_COL_SHIFT(ch) (0 + 2 * (ch))
-#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch))
-
-/* Get sdram size decode from reg */
-size_t rockchip_sdram_size(phys_addr_t reg);
-
-/* Called by U-Boot board_init_r for Rockchip SoCs */
-int dram_init(void);
-
-#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG)
-inline void sdram_print_dram_type(unsigned char dramtype)
-{
-}
-
-inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
- struct sdram_base_params *base)
-{
-}
-
-inline void sdram_print_stride(unsigned int stride)
-{
-}
-#else
-void sdram_print_dram_type(unsigned char dramtype);
-void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
- struct sdram_base_params *base);
-void sdram_print_stride(unsigned int stride);
-#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
-
-#endif
obj-$(CONFIG_MISC_INIT_R) += misc.o
endif
-obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
+obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
#if !CONFIG_IS_ENABLED(RAM)
/*
* When CONFIG_RAM is enabled, the dram_init() function is implemented
- * in sdram_common.c.
+ * in sdram.c.
*/
int dram_init(void)
{
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/pmu_rk3288.h>
#include <asm/arch-rockchip/qos_rk3288.h>
-#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram.h>
DECLARE_GLOBAL_DATA_PTR;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/sdram.h>
+#include <dm/uclass-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024)
+
+struct tos_parameter_t {
+ u32 version;
+ u32 checksum;
+ struct {
+ char name[8];
+ s64 phy_addr;
+ u32 size;
+ u32 flags;
+ } tee_mem;
+ struct {
+ char name[8];
+ s64 phy_addr;
+ u32 size;
+ u32 flags;
+ } drm_mem;
+ s64 reserve[8];
+};
+
+int dram_init_banksize(void)
+{
+ size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
+ gd->ram_top);
+
+#ifdef CONFIG_ARM64
+ /* Reserve 0x200000 for ATF bl31 */
+ gd->bd->bi_dram[0].start = 0x200000;
+ gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
+#else
+#ifdef CONFIG_SPL_OPTEE
+ struct tos_parameter_t *tos_parameter;
+
+ tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
+ TRUST_PARAMETER_OFFSET);
+
+ if (tos_parameter->tee_mem.flags == 1) {
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
+ - CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
+ tos_parameter->tee_mem.size;
+ gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+ + top - gd->bd->bi_dram[1].start;
+ } else {
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x8400000;
+ /* Reserve 32M for OPTEE with TA */
+ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+ + gd->bd->bi_dram[0].size + 0x2000000;
+ gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+ + top - gd->bd->bi_dram[1].start;
+ }
+#else
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
+#endif
+#endif
+
+ return 0;
+}
+
+size_t rockchip_sdram_size(phys_addr_t reg)
+{
+ u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
+ size_t chipsize_mb = 0;
+ size_t size_mb = 0;
+ u32 ch;
+
+ u32 sys_reg = readl(reg);
+ u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT)
+ & SYS_REG_NUM_CH_MASK);
+
+ debug("%s %x %x\n", __func__, (u32)reg, sys_reg);
+ for (ch = 0; ch < ch_num; ch++) {
+ rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
+ SYS_REG_RANK_MASK);
+ col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
+ bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
+ cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
+ SYS_REG_CS0_ROW_MASK);
+ cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
+ SYS_REG_CS1_ROW_MASK);
+ bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
+ SYS_REG_BW_MASK));
+ row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
+ SYS_REG_ROW_3_4_MASK;
+
+ chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
+
+ if (rank > 1)
+ chipsize_mb += chipsize_mb >> (cs0_row - cs1_row);
+ if (row_3_4)
+ chipsize_mb = chipsize_mb * 3 / 4;
+ size_mb += chipsize_mb;
+ debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n",
+ rank, col, bk, cs0_row, bw, row_3_4);
+ }
+
+ /*
+ * This is workaround for issue we can't get correct size for 4GB ram
+ * in 32bit system and available before we really need ram space
+ * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
+ * The size of 4GB is '0x1 00000000', and this value will be truncated
+ * to 0 in 32bit system, and system can not get correct ram size.
+ * Rockchip SoCs reserve a blob of space for peripheral near 4GB,
+ * and we are now setting SDRAM_MAX_SIZE as max available space for
+ * ram in 4GB, so we can use this directly to workaround the issue.
+ * TODO:
+ * 1. update correct value for SDRAM_MAX_SIZE as what dram
+ * controller sees.
+ * 2. update board_get_usable_ram_top() and dram_init_banksize()
+ * to reserve memory for peripheral space after previous update.
+ */
+ if (size_mb > (SDRAM_MAX_SIZE >> 20))
+ size_mb = (SDRAM_MAX_SIZE >> 20);
+
+ return (size_t)size_mb << 20;
+}
+
+int dram_init(void)
+{
+ struct ram_info ram;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+ ret = ram_get_info(dev, &ram);
+ if (ret) {
+ debug("Cannot get DRAM size: %d\n", ret);
+ return ret;
+ }
+ gd->ram_size = ram.size;
+ debug("SDRAM base=%lx, size=%lx\n",
+ (unsigned long)ram.base, (unsigned long)ram.size);
+
+ return 0;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
+
+ return (gd->ram_top > top) ? top : gd->ram_top;
+}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
- */
-
-#include <common.h>
-#include <dm.h>
-#include <ram.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/sdram_common.h>
-#include <dm/uclass-internal.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024)
-
-struct tos_parameter_t {
- u32 version;
- u32 checksum;
- struct {
- char name[8];
- s64 phy_addr;
- u32 size;
- u32 flags;
- } tee_mem;
- struct {
- char name[8];
- s64 phy_addr;
- u32 size;
- u32 flags;
- } drm_mem;
- s64 reserve[8];
-};
-
-int dram_init_banksize(void)
-{
- size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
- gd->ram_top);
-
-#ifdef CONFIG_ARM64
- /* Reserve 0x200000 for ATF bl31 */
- gd->bd->bi_dram[0].start = 0x200000;
- gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
-#else
-#ifdef CONFIG_SPL_OPTEE
- struct tos_parameter_t *tos_parameter;
-
- tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
- TRUST_PARAMETER_OFFSET);
-
- if (tos_parameter->tee_mem.flags == 1) {
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
- - CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
- tos_parameter->tee_mem.size;
- gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
- + top - gd->bd->bi_dram[1].start;
- } else {
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = 0x8400000;
- /* Reserve 32M for OPTEE with TA */
- gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
- + gd->bd->bi_dram[0].size + 0x2000000;
- gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
- + top - gd->bd->bi_dram[1].start;
- }
-#else
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
-#endif
-#endif
-
- return 0;
-}
-
-size_t rockchip_sdram_size(phys_addr_t reg)
-{
- u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
- size_t chipsize_mb = 0;
- size_t size_mb = 0;
- u32 ch;
-
- u32 sys_reg = readl(reg);
- u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT)
- & SYS_REG_NUM_CH_MASK);
-
- debug("%s %x %x\n", __func__, (u32)reg, sys_reg);
- for (ch = 0; ch < ch_num; ch++) {
- rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
- SYS_REG_RANK_MASK);
- col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
- bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
- cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
- SYS_REG_CS0_ROW_MASK);
- cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
- SYS_REG_CS1_ROW_MASK);
- bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
- SYS_REG_BW_MASK));
- row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
- SYS_REG_ROW_3_4_MASK;
-
- chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
-
- if (rank > 1)
- chipsize_mb += chipsize_mb >> (cs0_row - cs1_row);
- if (row_3_4)
- chipsize_mb = chipsize_mb * 3 / 4;
- size_mb += chipsize_mb;
- debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n",
- rank, col, bk, cs0_row, bw, row_3_4);
- }
-
- /*
- * This is workaround for issue we can't get correct size for 4GB ram
- * in 32bit system and available before we really need ram space
- * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
- * The size of 4GB is '0x1 00000000', and this value will be truncated
- * to 0 in 32bit system, and system can not get correct ram size.
- * Rockchip SoCs reserve a blob of space for peripheral near 4GB,
- * and we are now setting SDRAM_MAX_SIZE as max available space for
- * ram in 4GB, so we can use this directly to workaround the issue.
- * TODO:
- * 1. update correct value for SDRAM_MAX_SIZE as what dram
- * controller sees.
- * 2. update board_get_usable_ram_top() and dram_init_banksize()
- * to reserve memory for peripheral space after previous update.
- */
- if (size_mb > (SDRAM_MAX_SIZE >> 20))
- size_mb = (SDRAM_MAX_SIZE >> 20);
-
- return (size_t)size_mb << 20;
-}
-
-int dram_init(void)
-{
- struct ram_info ram;
- struct udevice *dev;
- int ret;
-
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- return ret;
- }
- ret = ram_get_info(dev, &ram);
- if (ret) {
- debug("Cannot get DRAM size: %d\n", ret);
- return ret;
- }
- gd->ram_size = ram.size;
- debug("SDRAM base=%lx, size=%lx\n",
- (unsigned long)ram.base, (unsigned long)ram.size);
-
- return 0;
-}
-
-ulong board_get_usable_ram_top(ulong total_size)
-{
- unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
-
- return (gd->ram_top > top) ? top : gd->ram_top;
-}
#include <asm/arch-rockchip/cru_rk3368.h>
#include <asm/arch-rockchip/grf_rk3368.h>
#include <asm/arch-rockchip/ddr_rk3368.h>
+#include <asm/arch-rockchip/sdram.h>
#include <asm/arch-rockchip/sdram_rk3288.h>
-#include <asm/arch-rockchip/sdram_common.h>
struct dram_info {
struct ram_info info;
#include <common.h>
#include <debug_uart.h>
-#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram.h>
void sdram_print_dram_type(unsigned char dramtype)
{
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/grf_rk3128.h>
-#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram.h>
struct dram_info {
struct ram_info info;
#include <asm/arch-rockchip/ddr_rk3188.h>
#include <asm/arch-rockchip/grf_rk3188.h>
#include <asm/arch-rockchip/pmu_rk3188.h>
+#include <asm/arch-rockchip/sdram.h>
#include <asm/arch-rockchip/sdram_rk3288.h>
-#include <asm/arch-rockchip/sdram_common.h>
#include <linux/err.h>
struct chan_info {
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/sdram_rk322x.h>
#include <asm/arch-rockchip/uart.h>
-#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram.h>
#include <asm/types.h>
#include <linux/err.h>
#include <asm/arch-rockchip/ddr_rk3288.h>
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/pmu_rk3288.h>
+#include <asm/arch-rockchip/sdram.h>
#include <asm/arch-rockchip/sdram_rk3288.h>
-#include <asm/arch-rockchip/sdram_common.h>
#include <linux/err.h>
#include <power/regulator.h>
#include <power/rk8xx_pmic.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3328.h>
#include <asm/arch-rockchip/grf_rk3328.h>
-#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram.h>
#include <asm/arch-rockchip/sdram_rk3328.h>
#include <asm/arch-rockchip/uart.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/pmu_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram.h>
#include <asm/arch-rockchip/sdram_rk3399.h>
#include <linux/err.h>
#include <time.h>
projects / oweals / u-boot.git / commitdiff