and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
-config ROCKCHIP_SPL_HDR
- string "Header of rockchip's spl loader"
- help
- Rockchip's bootrom requires the spl loader to start with a 4-bytes
- header. The content of this header depends on the chip type.
-
-config ROCKCHIP_MAX_SPL_SIZE
- hex "Max size of rockchip's spl loader"
- help
- Different chip may have different sram size. And if we want to jump
- back to the bootrom after spl, we may need to reserve some sram space
- for the bootrom.
- The max spl loader size should be sram size minus reserved
- size(if needed)
-
config SYS_MALLOC_F
default y
config SYS_MALLOC_F_LEN
default 0x400
-config ROCKCHIP_SPL_HDR
- default "RK30"
-
-config ROCKCHIP_MAX_SPL_SIZE
- default 0x1000
-
config ROCKCHIP_COMMON
bool "Support rk common fuction"
WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
the keyboard and battery functions.
-config ROCKCHIP_SPL_HDR
- default "RK32"
-
-config ROCKCHIP_MAX_SPL_SIZE
- default 0x8000
-
config SYS_SOC
default "rockchip"
rsa-sign.o rsa-verify.o rsa-checksum.o \
rsa-mod-exp.o)
-ROCKCHIP_OBS = $(if $(CONFIG_ARCH_ROCKCHIP),lib/rc4.o rkcommon.o rkimage.o rksd.o,)
+ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o
# common objs for dumpimage and mkimage
dumpimage-mkimage-objs := aisimage.o \
# TODO(sjg@chromium.org): Is this correct on Mac OS?
-ifneq ($(CONFIG_ARCH_ROCKCHIP),)
-HOST_EXTRACFLAGS += \
- -DCONFIG_ROCKCHIP_MAX_SPL_SIZE=$(CONFIG_ROCKCHIP_MAX_SPL_SIZE) \
- -DCONFIG_ROCKCHIP_SPL_HDR="\"$(CONFIG_ROCKCHIP_SPL_HDR)\""
-endif
-
ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
# the mxsimage support within tools/mxsimage.c .
{
struct header0_info *hdr;
- if (file_size > CONFIG_ROCKCHIP_MAX_SPL_SIZE)
+ if (file_size > RK_MAX_CODE1_SIZE)
return -ENOSPC;
memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
RK_BLK_SIZE = 512,
RK_INIT_OFFSET = 4,
RK_MAX_BOOT_SIZE = 512 << 10,
+ RK_MAX_CODE1_SIZE = 32 << 10,
};
/**
static void rkimage_set_header(void *buf, struct stat *sbuf, int ifd,
struct image_tool_params *params)
{
- memcpy(buf, CONFIG_ROCKCHIP_SPL_HDR, 4);
+ memcpy(buf, "RK32", 4);
}
static int rkimage_extract_subimage(void *buf, struct image_tool_params *params)
size);
}
- memcpy(buf + RKSD_SPL_HDR_START, CONFIG_ROCKCHIP_SPL_HDR, 4);
+ memcpy(buf + RKSD_SPL_HDR_START, "RK32", 4);
}
static int rksd_extract_subimage(void *buf, struct image_tool_params *params)
{
int pad_size;
- pad_size = RKSD_SPL_HDR_START + CONFIG_ROCKCHIP_MAX_SPL_SIZE;
+ pad_size = RKSD_SPL_HDR_START + RK_MAX_CODE1_SIZE;
debug("pad_size %x\n", pad_size);
return pad_size - params->file_size;
size);
}
- memcpy(buf + RKSPI_SPL_HDR_START, CONFIG_ROCKCHIP_SPL_HDR, 4);
+ memcpy(buf + RKSPI_SPL_HDR_START, "RK32", 4);
/*
* Spread the image out so we only use the first 2KB of each 4KB
{
int pad_size;
- pad_size = (CONFIG_ROCKCHIP_MAX_SPL_SIZE + 0x7ff) / 0x800 * 0x800;
+ pad_size = (RK_MAX_CODE1_SIZE + 0x7ff) / 0x800 * 0x800;
params->orig_file_size = pad_size;
/* We will double the image size due to the SPI format */