Fixed mips_io_port_base build errors.

This patch has been sent on:
- 29 Sep 2007

Although mips_io_port_base is currently a part of IDE command, it is quite
fundamental for MIPS I/O port access such as in[bwl] and out[bwl]. So move
it to MIPS general part, and introduce `set_io_port_base()' from Linux.

This patch is triggered by multiple definition of `mips_io_port_base' build
error on gth2 (and tb0229 also needs this fix.)

board/gth2/libgth2.a(gth2.o): In function `log_serial_char':
/home/skuribay/devel/u-boot.git/board/gth2/gth2.c:47: multiple definition of `mips_io_port_base'
common/libcommon.a(cmd_ide.o):/home/skuribay/devel/u-boot.git/common/cmd_ide.c:712: first defined here
make: *** [u-boot] Error 1

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c
index d29e8d591e31146b0fb5ea6cf56b042d5d6cac0f..a13eeeb1232306ed84b219493d4367a50d071f4c 100644 (file)
--- a/board/dbau1x00/dbau1x00.c
+++ b/board/dbau1x00/dbau1x00.c
@@ -25,6 +25,7 @@
 #include <command.h>
 #include <asm/au1x00.h>
 #include <asm/mipsregs.h>
+#include <asm/io.h>
 
 long int initdram(int board_type)
 {
@@ -77,6 +78,9 @@ int checkboard (void)
        default:
                printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
        }
+
+       set_io_port_base(0);
+
 #ifdef CONFIG_IDE_PCMCIA
        /* Enable 3.3 V on slot 0 ( VCC )
           No 5V */

diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c
index ffeaf587b56bf5093b13e212466fe425cca4aa6e..1593f02109a6afc9d0aac375191c464ea17388a6 100644 (file)
--- a/board/gth2/gth2.c
+++ b/board/gth2/gth2.c
@@ -26,14 +26,13 @@
 #include <asm/au1x00.h>
 #include <asm/addrspace.h>
 #include <asm/mipsregs.h>
+#include <asm/io.h>
 #include <watchdog.h>
 
 #include "ee_access.h"
 
 static int wdi_status = 0;
 
-unsigned long mips_io_port_base = 0;
-
 #define SDRAM_SIZE ((64*1024*1024)-(12*4096))
 
 
@@ -147,6 +146,9 @@ int checkboard (void)
        default:
                printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
        }
+
+       set_io_port_base(0);
+
 #ifdef CONFIG_IDE_PCMCIA
        /* PCMCIA is on a 36 bit physical address.
           We need to map it into a 32 bit addresses */

diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c
index b5d9e0049270711adbd134a59f3841f2f9e326c7..dbf0ecc5af3d1d56bfbd9b16c18a2ea27c16ce94 100644 (file)
--- a/board/incaip/incaip.c
+++ b/board/incaip/incaip.c
@@ -25,7 +25,7 @@
 #include <command.h>
 #include <asm/addrspace.h>
 #include <asm/inca-ip.h>
-
+#include <asm/io.h>
 
 extern uint incaip_get_cpuclk(void);
 
@@ -85,7 +85,6 @@ long int initdram(int board_type)
 
 int checkboard (void)
 {
-
        unsigned long chipid = *INCA_IP_WDT_CHIPID;
        int part_num;
 
@@ -107,5 +106,7 @@ int checkboard (void)
 
        printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000);
 
+       set_io_port_base(0);
+
        return 0;
 }

diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c
index 40ac2a4d7cd719812c90c13c3a23ab15787e4470..95b7d8246ee480505f638b4fc6af9c2ea8d37c29 100644 (file)
--- a/board/pb1x00/pb1x00.c
+++ b/board/pb1x00/pb1x00.c
@@ -25,6 +25,7 @@
 #include <command.h>
 #include <asm/au1x00.h>
 #include <asm/mipsregs.h>
+#include <asm/io.h>
 
 long int initdram(int board_type)
 {
@@ -69,6 +70,9 @@ int checkboard (void)
        default:
                printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
        }
+
+       set_io_port_base(0);
+
 #if defined(CONFIG_IDE_PCMCIA) && 0
        /* Enable 3.3 V on slot 0 ( VCC )
           No 5V */

diff --git a/board/purple/purple.c b/board/purple/purple.c
index 4c3e5b44b5303ed161d30fe90a885658e5755f2d..74718afb4897d4e690a23ffda5243ed3189d0389 100644 (file)
--- a/board/purple/purple.c
+++ b/board/purple/purple.c
@@ -26,6 +26,7 @@
 #include <asm/inca-ip.h>
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>
+#include <asm/io.h>
 #include <asm/addrspace.h>
 #include <asm/cacheops.h>
 
@@ -145,6 +146,8 @@ int checkboard (void)
 
        printf("CPU Speed %d MHz\n", CPU_CLOCK_RATE/1000000);
 
+       set_io_port_base(0);
+
        return 0;
 }
 

diff --git a/board/tb0229/tb0229.c b/board/tb0229/tb0229.c
index e7914bd15bd7c9a94894013bb5911f67f55bacb8..61c2e9bd36606f00872c90bd082f12b1f223513e 100644 (file)
--- a/board/tb0229/tb0229.c
+++ b/board/tb0229/tb0229.c
@@ -13,10 +13,9 @@
 #include <command.h>
 #include <asm/addrspace.h>
 #include <asm/inca-ip.h>
+#include <asm/io.h>
 #include <pci.h>
 
-unsigned long mips_io_port_base = 0;
-
 #if defined(CONFIG_PCI)
 static struct pci_controller hose;
 
@@ -26,17 +25,17 @@ void pci_init_board (void)
 }
 #endif
 
-
 long int initdram(int board_type)
 {
        return get_ram_size (CFG_SDRAM_BASE, 0x8000000);
 }
 
-
 int checkboard (void)
 {
        printf("Board: TANBAC TB0229 ");
        printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000);
 
+       set_io_port_base(0);
+
        return 0;
 }

diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index 27cecac4eed9f4d9e0d6a9a1cabc68d8f0ec01d9..2202009f5f22aff7be45cab29d538d7824eb2df6 100644 (file)
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -54,10 +54,6 @@
 
 #ifndef __PPC__
 #include <asm/io.h>
-#ifdef __MIPS__
-/* Macros depend on this variable */
-unsigned long mips_io_port_base = 0;
-#endif
 #endif
 
 #ifdef CONFIG_IDE_8xx_DIRECT

diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index cd4d5dc9d9e8e4ff158e18f89ceeb268d6e495e9..1e060f7c31d7bfb01b14d34bfd02324ef7c828c4 100644 (file)
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -71,7 +71,21 @@
  * instruction, so the lower 16 bits must be zero.  Should be true on
  * on any sane architecture; generic code does not use this assumption.
  */
-extern unsigned long mips_io_port_base;
+extern const unsigned long mips_io_port_base;
+
+/*
+ * Gcc will generate code to load the value of mips_io_port_base after each
+ * function call which may be fairly wasteful in some cases.  So we don't
+ * play quite by the book.  We tell gcc mips_io_port_base is a long variable
+ * which solves the code generation issue.  Now we need to violate the
+ * aliasing rules a little to make initialization possible and finally we
+ * will need the barrier() to fight side effects of the aliasing chat.
+ * This trickery will eventually collapse under gcc's optimizer.  Oh well.
+ */
+static inline void set_io_port_base(unsigned long base)
+{
+       * (unsigned long *) &mips_io_port_base = base;
+}
 
 /*
  * Thanks to James van Artsdalen for a better timing-fix than

diff --git a/lib_mips/board.c b/lib_mips/board.c
index 91ccec04df76b04ed20816a212176a2857d8e040..c1a0acf46986e00e229be005c054f46fba497182 100644 (file)
--- a/lib_mips/board.c
+++ b/lib_mips/board.c
@@ -62,6 +62,11 @@ static ulong mem_malloc_start;
 static ulong mem_malloc_end;
 static ulong mem_malloc_brk;
 
+/*
+ * mips_io_port_base is the begin of the address space to which x86 style
+ * I/O ports are mapped.
+ */
+unsigned long mips_io_port_base = -1;
 
 /*
  * The Malloc area is immediately below the monitor copy in DRAM