for (i = 0; i < RX_BUF; i++) {
priv->rx_bd[i].status = 0xF0000000;
priv->rx_bd[i].addr =
- ((u32)(priv->rxbuffers) +
+ ((ulong)(priv->rxbuffers) +
(i * PKTSIZE_ALIGN));
}
/* WRAP bit to last BD */
priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
/* Write RxBDs to IP */
- writel((u32)priv->rx_bd, ®s->rxqbase);
+ writel((ulong)priv->rx_bd, ®s->rxqbase);
/* Setup for DMA Configuration register */
writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
/* setup BD */
- writel((u32)priv->tx_bd, ®s->txqbase);
+ writel((ulong)priv->tx_bd, ®s->txqbase);
/* Setup Tx BD */
memset(priv->tx_bd, 0, sizeof(struct emac_bd));
- priv->tx_bd->addr = (u32)ptr;
+ priv->tx_bd->addr = (ulong)ptr;
priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
ZYNQ_GEM_TXBUF_LAST_MASK |
ZYNQ_GEM_TXBUF_WRAP_MASK;
- addr = (u32) ptr;
+ addr = (ulong) ptr;
addr &= ~(ARCH_DMA_MINALIGN - 1);
size = roundup(len, ARCH_DMA_MINALIGN);
flush_dcache_range(addr, addr + size);
- addr = (u32)priv->rxbuffers;
+ addr = (ulong)priv->rxbuffers;
addr &= ~(ARCH_DMA_MINALIGN - 1);
size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
flush_dcache_range(addr, addr + size);
u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
addr &= ~(ARCH_DMA_MINALIGN - 1);
- net_process_received_packet((u8 *)addr, frame_len);
+ net_process_received_packet((u8 *)(ulong)addr, frame_len);
if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
priv->rx_first_buf = priv->rxbd_current;
/* Initialize the bd spaces for tx and rx bd's */
priv->tx_bd = (struct emac_bd *)bd_space;
- priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE);
+ priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
priv->phyaddr = phy_addr;
priv->emio = emio;