ulong cpu_init_f(void)
{
- ulong flag = 0;
extern void m8560_cpm_reset (void);
#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
(defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
in_be32(&gur->dcsrcr);
#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-#ifdef CONFIG_DEEP_SLEEP
- /* disable the console if boot from deep sleep */
- if (in_be32(&gur->scrtsr[0]) & (1 << 3))
- flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
-#endif
-#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
fsl_erratum_a007212_workaround();
#endif
- return flag;
+ return 0;
}
/* Implement a dummy function for those platforms w/o SERDES */
#ifdef CONFIG_PRAM
ulong reg;
#endif
-#ifdef CONFIG_DEEP_SLEEP
- const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
- u32 start_addr;
- typedef void (*func_t)(void);
- func_t kernel_resume;
-#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
if ((*init_fnc_ptr) () != 0)
hang();
-#ifdef CONFIG_DEEP_SLEEP
- /* Jump to kernel in deep sleep case */
- if (in_be32(&gur->scrtsr[0]) & (1 << 3)) {
- l2cache_init();
-#if defined(CONFIG_RAMBOOT_PBL)
- disable_cpc_sram();
-#endif
- enable_cpc();
- start_addr = in_be32(&scfg->sparecr[1]);
- kernel_resume = (func_t)start_addr;
- kernel_resume();
- }
-#endif
-
#ifdef CONFIG_POST
post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(NULL));