P1020: dts: Added PCIe DT nodes

P1020 integrated 2 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
index e1a4f500a678fb7d3e7840e1ccfeeb320578ec96..1e5e67804b85cdf2c7a4be32a7b4be0e78973bdc 100644 (file)
--- a/arch/powerpc/dts/p1020-post.dtsi
+++ b/arch/powerpc/dts/p1020-post.dtsi
@@ -25,3 +25,23 @@
                last-interrupt-source = <255>;
        };
 };
+
+/* PCIe controller base address 0x9000 */
+&pci1 {
+       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+       law_trgt_if = <1>;
+       #address-cells = <3>;
+       #size-cells = <2>;
+       device_type = "pci";
+       bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0xa000 */
+&pci0 {
+       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+       law_trgt_if = <2>;
+       #address-cells = <3>;
+       #size-cells = <2>;
+       device_type = "pci";
+       bus-range = <0x0 0xff>;
+};

diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts
index fd68b8b440b84bb22b08a1bae290d07f43cd46ab..7ebaa619df4a9964222fd3884108938038548532 100644 (file)
--- a/arch/powerpc/dts/p1020rdb-pc.dts
+++ b/arch/powerpc/dts/p1020rdb-pc.dts
@@ -18,6 +18,18 @@
        soc: soc@ffe00000 {
                ranges = <0x0 0x0 0xffe00000 0x100000>;
        };
+
+       pci1: pcie@ffe09000 {
+               reg = <0x0 0xffe09000 0x0 0x1000>;      /* registers */
+               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000   /* downstream I/O */
+                         0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+       };
+
+       pci0: pcie@ffe0a000 {
+               reg = <0x0 0xffe0a000 0x0 0x1000>;      /* registers */
+               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
+                         0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+       };
 };
 
 /include/ "p1020-post.dtsi"

diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts
index a23d031eee7b3e74d05f9c5850b72cf5bf8983a7..c0e5ef4cf42fc0025d34c85d2072768c764b39a6 100644 (file)
--- a/arch/powerpc/dts/p1020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts
@@ -18,6 +18,18 @@
        soc: soc@fffe00000 {
                ranges = <0x0 0xf 0xffe00000 0x100000>;
        };
+
+       pci1: pcie@fffe09000 {
+               reg = <0xf 0xffe09000 0x0 0x1000>;      /* registers */
+               ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000   /* downstream I/O */
+                         0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+       };
+
+       pci0: pcie@fffe0a000 {
+               reg = <0xf 0xffe0a000 0x0 0x1000>;      /* registers */
+               ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000   /* downstream I/O */
+                         0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+       };
 };
 
 /include/ "p1020-post.dtsi"

diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts
index 81f25a3866ae072af8519c45e4150feaa42cfcee..21174a09be550abd5d844192177e0644930b5a3b 100644 (file)
--- a/arch/powerpc/dts/p1020rdb-pd.dts
+++ b/arch/powerpc/dts/p1020rdb-pd.dts
@@ -18,6 +18,18 @@
        soc: soc@ffe00000 {
                ranges = <0x0 0x0 0xffe00000 0x100000>;
        };
+
+       pci1: pcie@ffe09000 {
+               reg = <0x0 0xffe09000 0x0 0x1000>;      /* registers */
+               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000   /* downstream I/O */
+                         0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+       };
+
+       pci0: pcie@ffe0a000 {
+               reg = <0x0 0xffe0a000 0x0 0x1000>;      /* registers */
+               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
+                         0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+       };
 };
 
 /include/ "p1020-post.dtsi"