AT91RM9200DK at91rm9200
+Po-Yu Chuang <ratbert@faraday-tech.com>
+
+ a320evb FA526 (ARM920T-like) (a320 SoC)
+
George G. Davis <gdavis@mvista.com>
assabet SA1100
B2 ARM7TDMI (S3C44B0X)
+Nick Thompson <nick.thompson@gefanuc.com>
+
+ da830evm ARM926EJS (DA830/OMAP-L137)
+
Albin Tonnerre <albin.tonnerre@free-electrons.com>
sbc35_a9g20 ARM926EJS (AT91SAM9G20 SoC)
#########################################################################
LIST_ARM9=" \
+ a320evb \
ap920t \
ap922_XA10 \
ap926ejs \
cp926ejs \
cp946es \
cp966 \
+ da830evm \
imx27lite \
lpd7a400 \
mv88f6281gtw_ge \
## ARM92xT Systems
#########################################################################
+a320evb_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm920t a320evb faraday a320
+
#########################################################################
## Atmel AT91RM9200 Systems
#########################################################################
cp1026_config: unconfig
@board/armltd/integrator/split_by_variant.sh cp $@
+da830evm_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs da830evm davinci davinci
+
davinci_dvevm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dvevm davinci davinci
# bit12-11: TW2W
# bit31-13: zero required
-DATA 0xFFD01410 0x00000099 # DDR Address Control
-# bit1-0: 01, Cs0width=x16
-# bit3-2: 10, Cs0size=512Mb
-# bit5-4: 01, Cs1width=x16
-# bit7-6: 10, Cs1size=512Mb
+DATA 0xFFD01410 0x000000cc # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs1width=x8
+# bit7-6: 11, Cs1size=1Gb
# bit9-8: 00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
/*
* Miscelaneous DaVinci functions.
*
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
* Copyright (C) 2004 Texas Instruments.
#include <i2c.h>
#include <net.h>
#include <asm/arch/hardware.h>
-
+#include <asm/io.h>
+#include "misc.h"
DECLARE_GLOBAL_DATA_PTR;
}
#endif /* DAVINCI_EMAC */
+
+/*
+ * Change the setting of a pin multiplexer field.
+ *
+ * Takes an array of pinmux settings similar to:
+ *
+ * struct pinmux_config uart_pins[] = {
+ * { &davinci_syscfg_regs->pinmux[8], 2, 7 },
+ * { &davinci_syscfg_regs->pinmux[9], 2, 0 }
+ * };
+ *
+ * Stepping through the array, each pinmux[n] register has the given value
+ * set in the pin mux field specified.
+ *
+ * The number of pins in the array must be passed (ARRAY_SIZE can provide
+ * this value conveniently).
+ *
+ * Returns 0 if all field numbers and values are in the correct range,
+ * else returns -1.
+ */
+int davinci_configure_pin_mux(const struct pinmux_config *pins,
+ const int n_pins)
+{
+ int i;
+
+ /* check for invalid pinmux values */
+ for (i = 0; i < n_pins; i++) {
+ if (pins[i].field >= PIN_MUX_NUM_FIELDS ||
+ (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0)
+ return -1;
+ }
+
+ /* configure the pinmuxes */
+ for (i = 0; i < n_pins; i++) {
+ const int offset = pins[i].field * PIN_MUX_FIELD_SIZE;
+ const unsigned int value = pins[i].value << offset;
+ const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
+ const dv_reg *mux = pins[i].mux;
+
+ writel(value | (readl(mux) & (~mask)), mux);
+ }
+
+ return 0;
+}
#ifndef __MISC_H
#define __MISC_H
+/* pin muxer definitions */
+#define PIN_MUX_NUM_FIELDS 8 /* Per register */
+#define PIN_MUX_FIELD_SIZE 4 /* n in bits */
+#define PIN_MUX_FIELD_MASK ((1 << PIN_MUX_FIELD_SIZE) - 1)
+
+/* pin definition */
+struct pinmux_config {
+ dv_reg *mux; /* Address of mux register */
+ unsigned char value; /* Value to set in field */
+ unsigned char field; /* field number */
+};
int dvevm_read_mac_address(uint8_t *buf);
void dv_configure_mac_address(uint8_t *rom_enetaddr);
+int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
#endif /* __MISC_H */
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := da830evm.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# Texas Instruments DA8xx EVM board (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# DA8xx EVM has 1 bank of 64 MB SDRAM (2 16Meg x16 chips).
+# Physical Address:
+# C000'0000 to C400'0000
+#
+# Linux-Kernel is expected to be at C000'8000, entry C000'8000
+# (mem base + reserved)
+#
+# we load ourself to C108 '0000
+
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+TEXT_BASE = 0xC1080000
--- /dev/null
+/*
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ *
+ * Base on code from TI. Original Notices follow:
+ *
+ * (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
+ *
+ * Modified for DA8xx EVM.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * -----------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include "../common/misc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define pinmux &davinci_syscfg_regs->pinmux
+
+#ifdef CONFIG_SPI_FLASH
+/* SPI0 pin muxer settings */
+const struct pinmux_config spi0_pins[] = {
+ { pinmux[7], 1, 3 },
+ { pinmux[7], 1, 4 },
+ { pinmux[7], 1, 5 },
+ { pinmux[7], 1, 6 },
+ { pinmux[7], 1, 7 }
+};
+#endif
+
+/* UART pin muxer settings */
+const struct pinmux_config uart_pins[] = {
+ { pinmux[8], 2, 7 },
+ { pinmux[9], 2, 0 }
+};
+
+/* I2C pin muxer settings */
+const struct pinmux_config i2c_pins[] = {
+ { pinmux[9], 2, 3 },
+ { pinmux[9], 2, 4 }
+};
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+ /*
+ * Mask all IRQs by clearing the global enable and setting
+ * the enable clear for all the 90 interrupts.
+ */
+
+ writel(0, &davinci_aintc_regs->ger);
+
+ writel(0, &davinci_aintc_regs->hier);
+
+ writel(0xffffffff, &davinci_aintc_regs->ecr1);
+ writel(0xffffffff, &davinci_aintc_regs->ecr2);
+ writel(0xffffffff, &davinci_aintc_regs->ecr3);
+#endif
+
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /*
+ * Power on required peripherals
+ * ARM does not have access by default to PSC0 and PSC1
+ * assuming here that the DSP bootloader has set the IOPU
+ * such that PSC access is available to ARM
+ */
+ lpsc_on(DAVINCI_LPSC_AEMIF); /* NAND, NOR */
+ lpsc_on(DAVINCI_LPSC_SPI0); /* Serial Flash */
+ lpsc_on(DAVINCI_LPSC_EMAC); /* image download */
+ lpsc_on(DAVINCI_LPSC_UART2); /* console */
+ lpsc_on(DAVINCI_LPSC_GPIO);
+
+ /* setup the SUSPSRC for ARM to control emulation suspend */
+ writel(readl(&davinci_syscfg_regs->suspsrc) &
+ ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+ DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+ DAVINCI_SYSCFG_SUSPSRC_UART2),
+ &davinci_syscfg_regs->suspsrc);
+
+#ifdef CONFIG_SPI_FLASH
+ if (davinci_configure_pin_mux(spi0_pins, ARRAY_SIZE(spi0_pins)) != 0)
+ return 1;
+#endif
+
+ if (davinci_configure_pin_mux(uart_pins, ARRAY_SIZE(uart_pins)) != 0)
+ return 1;
+
+ if (davinci_configure_pin_mux(i2c_pins, ARRAY_SIZE(i2c_pins)) != 0)
+ return 1;
+
+ /* enable the console UART */
+ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+ DAVINCI_UART_PWREMU_MGMT_UTRST),
+ &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+ return(0);
+}
#include <common.h>
#include <asm/io.h>
+#include <nand.h>
+#include <asm/arch/nand_defs.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+#ifdef CONFIG_NAND_DAVINCI
+int board_nand_init(struct nand_chip *nand)
+{
+ davinci_nand_init(nand);
+
+ return 0;
+}
+#endif
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := a320evb.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <asm/arch/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_FARADAY;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ ftsmc020_init(); /* initialize Flash */
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_1;
+ unsigned long expected_size = PHYS_SDRAM_1_SIZE;
+ unsigned long actual_size;
+
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+ gd->bd->bi_dram[0].start = sdram_base;
+ gd->bd->bi_dram[0].size = actual_size;
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else
+ return 0;
+}
--- /dev/null
+#
+# (C) Copyright 2009 Faraday Technology
+# Po-Yu Chuang <ratbert@faraday-tech.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# Faraday A320 board with FA526/FA626TE/ARM926EJ-S cpus
+#
+# see http://www.faraday-tech.com/ for more information
+
+# A320 has 1 bank of 64 MB DRAM
+#
+# 1000'0000 to 1400'0000
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
+#
+# we load ourself to 13f8'0000
+#
+# download area is 1200'0000
+
+TEXT_BASE = 0x13f80000
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/macro.h>
+#include <asm/arch/ftsdmc020.h>
+
+/*
+ * parameters for the SDRAM controller
+ */
+#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
+#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
+#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
+#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
+#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
+
+#define TP0_D CONFIG_SYS_FTSDMC020_TP0
+#define TP1_D CONFIG_SYS_FTSDMC020_TP1
+#define CR_D1 FTSDMC020_CR_IPREC
+#define CR_D2 FTSDMC020_CR_ISMR
+#define CR_D3 FTSDMC020_CR_IREF
+
+#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \
+ FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
+#define ACR_D FTSDMC020_ACR_TOC(0x18)
+
+/*
+ * numeric 7 segment display
+ */
+.macro led, num
+ write32 CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+.macro wait_sdram
+ ldr r0, =CONFIG_FTSDMC020_BASE
+1:
+ ldr r1, [r0, #FTSDMC020_OFFSET_CR]
+ cmp r1, #0
+ bne 1b
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+ mov r11, lr
+
+ led 0x0
+
+ bl init_sdmc
+
+ led 0x1
+
+ /* everything is fine now */
+ mov lr, r11
+ mov pc, lr
+
+/*
+ * memory initialization
+ */
+init_sdmc:
+ led 0x10
+
+ /* set SDRAM register */
+
+ write32 TP0_A, TP0_D
+ led 0x11
+
+ write32 TP1_A, TP1_D
+ led 0x12
+
+ /* set to precharge */
+ write32 CR_A, CR_D1
+ led 0x13
+
+ wait_sdram
+ led 0x14
+
+ /* set mode register */
+ write32 CR_A, CR_D2
+ led 0x15
+
+ wait_sdram
+ led 0x16
+
+ /* set to refresh */
+ write32 CR_A, CR_D3
+ led 0x17
+
+ wait_sdram
+ led 0x18
+
+ write32 B0_BSR_A, B0_BSR_D
+ led 0x19
+
+ write32 ACR_A, ACR_D
+ led 0x1a
+
+ mov pc, lr
#include <common.h>
#include <netdev.h>
-#include <s3c2410.h>
+#include <asm/arch/s3c24x0_cpu.h>
#include <stdio_dev.h>
#include <i2c.h>
* Global routines used for VCMA9
*****************************************************************************/
-#include <s3c2410.h>
+#include <asm/arch/s3c24x0_cpu.h>
extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
/* VCMA9 PLD regsiters */
typedef struct {
- S3C24X0_REG8 ID;
- S3C24X0_REG8 NIC;
- S3C24X0_REG8 CAN;
- S3C24X0_REG8 MISC;
- S3C24X0_REG8 GPCD;
- S3C24X0_REG8 BOARD;
- S3C24X0_REG8 SDRAM;
+ u8 ID;
+ u8 NIC;
+ u8 CAN;
+ u8 MISC;
+ u8 GPCD;
+ u8 BOARD;
+ u8 SDRAM;
} /*__attribute__((__packed__))*/ VCMA9_PLD;
#define VCMA9_PLD_BASE 0x2C000100
MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)) /*GPIO_147,*/\
/*UART2_RX*/\
/*Serial Interface (Peripheral boot, Linux console, on AV connector)*/\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX*/\
+ /*RX pulled up to avoid noise when nothing is connected to serial port*/\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX*/\
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX*/\
/*LEDs (Controlled by OMAP)*/\
MUX_VAL(CP(MMC1_DAT6), (IDIS | PTD | DIS | M4)) /*GPIO_128*/\
#include <common.h>
#include <netdev.h>
-#include <s3c2400.h>
+#include <asm/arch/s3c24x0_cpu.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <netdev.h>
-#include <s3c2410.h>
+#include <asm/arch/s3c24x0_cpu.h>
DECLARE_GLOBAL_DATA_PTR;
#include <config.h>
#include <version.h>
-#include <s3c6400.h>
+#include <asm/arch/s3c6400.h>
#ifdef CONFIG_SERIAL1
#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
#include <common.h>
#include <netdev.h>
-#include <s3c6400.h>
+#include <asm/arch/s3c6400.h>
/* ------------------------------------------------------------------------- */
#define CS8900_Tacs 0x0 /* 0clk address set-up */
#include <common.h>
#include <netdev.h>
-#include <s3c2410.h>
+#include <asm/arch/s3c24x0_cpu.h>
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <common.h>
#include <command.h>
-#include <s3c2400.h>
+#include <asm/arch/s3c24x0_cpu.h>
#include <rtc.h>
/*
*/
#include <common.h>
-#include <s3c2400.h>
+#include <asm/arch/s3c24x0_cpu.h>
#include "rs485.h"
static void rs485_setbrg (void);
#ifndef _RS485_H_
#define _RS485_H_
-#include <s3c2400.h>
+#include <asm/arch/s3c24x0_cpu.h>
int rs485_init (void);
int rs485_getc (void);
#include <common.h>
#include <netdev.h>
#include <malloc.h>
-#include <s3c2400.h>
+#include <asm/arch/s3c24x0_cpu.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <exports.h>
#include <timestamp.h>
-#include <s3c2400.h>
+#include <asm/arch/s3c24x0_cpu.h>
#include "tsc2000.h"
#include "rs485.h"
*/
#include <common.h>
-#include <s3c2400.h>
+#include <asm/arch/s3c24x0_cpu.h>
#include <asm/io.h>
#include <div64.h>
#include "tsc2000.h"
#include <stdarg.h>
#include <linux/types.h>
#include <stdio_dev.h>
-#include <s3c2400.h>
+#include <asm/arch/s3c24x0_cpu.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <command.h>
-#include <s3c6400.h>
+#include <asm/arch/s3c6400.h>
#include <asm/system.h>
static void cache_flush (void);
*/
#include <config.h>
-#include <s3c6400.h>
+#include <asm/arch/s3c6400.h>
.globl mem_ctrl_asm_init
mem_ctrl_asm_init:
* MA 02111-1307 USA
*/
-#include <s3c6400.h>
+#include <asm/arch/s3c6400.h>
.globl reset_cpu
reset_cpu:
*/
#include <common.h>
-#include <s3c6400.h>
+#include <asm/arch/s3c6400.h>
#define APLL 0
#define MPLL 1
#include <common.h>
#include <asm/proc-armv/ptrace.h>
-#include <s3c6400.h>
+#include <asm/arch/s3c6400.h>
#include <div64.h>
static ulong timer_load_val;
#ifdef CONFIG_ENABLE_MMU
#include <asm/proc/domain.h>
#endif
-#include <s3c6400.h>
+#include <asm/arch/s3c6400.h>
#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
skip_hw_init:
/* Set up the stack */
stack_setup:
-#ifdef CONFIG_MEMORY_UPPER_CODE
- ldr sp, =(CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE - 0xc)
-#else
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
+ ldr r0, =CONFIG_SYS_UBOOT_BASE /* base of copy in DRAM */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
sub sp, r0, #12 /* leave 3 words for abort-stack */
-#endif
-
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+SOBJS += reset.o
+COBJS += timer.o
+COBJS += ftsmc020.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ftsmc020.h>
+
+struct ftsmc020_config {
+ unsigned int config;
+ unsigned int timing;
+};
+
+static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS;
+
+static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE;
+
+static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config *cfg)
+{
+ if (bank > 3) {
+ printf("bank # %u invalid\n", bank);
+ return;
+ }
+
+ writel(cfg->config, &smc->bank[bank].cr);
+ writel(cfg->timing, &smc->bank[bank].tpr);
+}
+
+void ftsmc020_init(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(config); i++)
+ ftsmc020_setup_bank(i, &config[i]);
+}
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+.global reset_cpu
+reset_cpu:
+ b reset_cpu
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ftpmu010.h>
+#include <asm/arch/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
+
+#define TIMER_CLOCK 32768
+#define TIMER_LOAD_VAL 0xffffffff
+
+int timer_init(void)
+{
+ unsigned int oscc;
+ unsigned int cr;
+
+ debug("%s()\n", __func__);
+
+ /* disable timers */
+ writel(0, &tmr->cr);
+
+ /*
+ * use 32768Hz oscillator for RTC, WDT, TIMER
+ */
+
+ /* enable the 32768Hz oscillator */
+ oscc = readl(&pmu->OSCC);
+ oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI);
+ writel(oscc, &pmu->OSCC);
+
+ /* wait until ready */
+ while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE))
+ ;
+
+ /* select 32768Hz oscillator */
+ oscc = readl(&pmu->OSCC);
+ oscc |= FTPMU010_OSCC_OSCL_RTCLSEL;
+ writel(oscc, &pmu->OSCC);
+
+ /* setup timer */
+ writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+ writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+ writel(0, &tmr->timer3_match1);
+ writel(0, &tmr->timer3_match2);
+
+ /* we don't want timer to issue interrupts */
+ writel(FTTMR010_TM3_MATCH1 |
+ FTTMR010_TM3_MATCH2 |
+ FTTMR010_TM3_OVERFLOW,
+ &tmr->interrupt_mask);
+
+ cr = readl(&tmr->cr);
+ cr |= FTTMR010_TM3_CLOCK; /* use external clock */
+ cr |= FTTMR010_TM3_ENABLE;
+ writel(cr, &tmr->cr);
+
+ /* init the timestamp and lastdec value */
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+ /* capure current decrementer value time */
+ lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+
+ debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+ debug("%s()\n", __func__);
+ reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+ /* current tick value */
+ ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+
+ debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+ if (lastdec >= now) {
+ /*
+ * normal mode (non roll)
+ * move stamp fordward with absoulte diff ticks
+ */
+ timestamp += lastdec - now;
+ } else {
+ /*
+ * we have overflow of the count down timer
+ *
+ * nts = ts + ld + (TLV - now)
+ * ts=old stamp, ld=time that passed before passing through -1
+ * (TLV-now) amount of time after passing though -1
+ * nts = new "advancing time stamp"...it could also roll and
+ * cause problems.
+ */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+
+ lastdec = now;
+
+ debug("%s() returns %lx\n", __func__, timestamp);
+
+ return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+ debug("%s(%lx)\n", __func__, base);
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ debug("%s(%lx)\n", __func__, t);
+ timestamp = t;
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay(unsigned long usec)
+{
+ long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+ unsigned long now, last = readl(&tmr->timer3_counter);
+
+ debug("%s(%lu)\n", __func__, usec);
+ while (tmo > 0) {
+ now = readl(&tmr->timer3_counter);
+ if (now > last) /* count down timer overflow */
+ tmo -= TIMER_LOAD_VAL + last - now;
+ else
+ tmo -= last - now;
+ last = now;
+ }
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ debug("%s()\n", __func__);
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ debug("%s()\n", __func__);
+ return CONFIG_SYS_HZ;
+}
#include <common.h>
-#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
-#endif
+#include <asm/arch/s3c24x0_cpu.h>
#include <asm/proc-armv/ptrace.h>
void do_irq (struct pt_regs *pt_regs)
*/
#include <common.h>
-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+#ifdef CONFIG_S3C24X0
#include <asm/io.h>
-
-#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
-#endif
+#include <asm/arch/s3c24x0_cpu.h>
#define MPLL 0
#define UPLL 1
return get_PLLCLK(UPLL);
}
-#endif /* defined(CONFIG_S3C2400) ||
- defined (CONFIG_S3C2410) ||
- defined (CONFIG_TRAB) */
+#endif /* CONFIG_S3C24X0 */
*/
#include <common.h>
-#if defined(CONFIG_S3C2400) || \
- defined(CONFIG_S3C2410) || \
- defined(CONFIG_TRAB)
+#ifdef CONFIG_S3C24X0
#include <asm/io.h>
-
-#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
-#endif
+#include <asm/arch/s3c24x0_cpu.h>
int timer_load_val = 0;
static ulong timer_clk;
/*NOTREACHED*/
}
-#endif /* defined(CONFIG_S3C2400) ||
- defined (CONFIG_S3C2410) ||
- defined (CONFIG_TRAB) */
+#endif /* CONFIG_S3C24X0 */
#include <common.h>
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
-
-#if defined(CONFIG_S3C2400)
-# include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-# include <s3c2410.h>
-#endif
+#if defined(CONFIG_USB_OHCI_NEW) && \
+ defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
+ defined(CONFIG_S3C24X0)
+#include <asm/arch/s3c24x0_cpu.h>
#include <asm/io.h>
int usb_cpu_init(void)
return 0;
}
-# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
-#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
+#endif /* defined(CONFIG_USB_OHCI_NEW) && \
+ defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
+ defined(CONFIG_S3C24X0) */
#include <common.h>
/* #include <pci.h> no PCI on the S3C24X0 */
-#ifdef CONFIG_USB_OHCI
-
-#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
-#endif
+#if defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0)
+#include <asm/arch/s3c24x0_cpu.h>
#include <asm/io.h>
#include <malloc.h>
#include <usb.h>
return 0;
}
-#endif /* CONFIG_USB_OHCI */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */
bne copyex
#endif
-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
+#ifdef CONFIG_S3C24X0
/* turn off the watchdog */
# if defined(CONFIG_S3C2400)
ldr r0, =CLKDIVN
mov r1, #3
str r1, [r0]
-#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
+#endif /* CONFIG_S3C24X0 */
/*
* we do sys-critical inits only at reboot,
#include <common.h>
#include <netdev.h>
#include <asm/arch/hardware.h>
-
+#include <asm/io.h>
/* offsets from PLL controller base */
#define PLLC_PLLCTL 0x100
#define DDR_PLLDIV PLLC_PLLDIV1
#endif
+#ifdef CONFIG_SOC_DA8XX
+const dv_reg * const sysdiv[7] = {
+ &davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2,
+ &davinci_pllc_regs->plldiv3, &davinci_pllc_regs->plldiv4,
+ &davinci_pllc_regs->plldiv5, &davinci_pllc_regs->plldiv6,
+ &davinci_pllc_regs->plldiv7
+};
+
+int clk_get(enum davinci_clk_ids id)
+{
+ int pre_div;
+ int pllm;
+ int post_div;
+ int pll_out;
+
+ pll_out = CONFIG_SYS_OSCIN_FREQ;
+
+ if (id == DAVINCI_AUXCLK_CLKID)
+ goto out;
+
+ /*
+ * Lets keep this simple. Combining operations can result in
+ * unexpected approximations
+ */
+ pre_div = (readl(&davinci_pllc_regs->prediv) &
+ DAVINCI_PLLC_DIV_MASK) + 1;
+ pllm = readl(&davinci_pllc_regs->pllm) + 1;
+
+ pll_out /= pre_div;
+ pll_out *= pllm;
+
+ if (id == DAVINCI_PLLM_CLKID)
+ goto out;
+
+ post_div = (readl(&davinci_pllc_regs->postdiv) &
+ DAVINCI_PLLC_DIV_MASK) + 1;
+
+ pll_out /= post_div;
+
+ if (id == DAVINCI_PLLC_CLKID)
+ goto out;
+
+ pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PLLC_DIV_MASK) + 1;
+
+out:
+ return pll_out;
+}
+#endif /* CONFIG_SOC_DA8XX */
#ifdef CONFIG_DISPLAY_CPUINFO
#include <common.h>
#include <asm/arch/hardware.h>
+#include <asm/io.h>
/*
* The PSC manages three inputs to a "module" which may be a peripheral or
/* Works on Always On power domain only (no PD argument) */
void lpsc_on(unsigned int id)
{
- dv_reg_p mdstat, mdctl;
+ dv_reg_p mdstat, mdctl, ptstat, ptcmd;
+#ifdef CONFIG_SOC_DA8XX
+ struct davinci_psc_regs *psc_regs;
+#endif
+#ifndef CONFIG_SOC_DA8XX
if (id >= DAVINCI_LPSC_GEM)
return; /* Don't work on DSP Power Domain */
mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
+ ptstat = REG_P(PSC_PTSTAT);
+ ptcmd = REG_P(PSC_PTCMD);
+#else
+ if (id < DAVINCI_LPSC_PSC1_BASE) {
+ if (id >= PSC_PSC0_MODULE_ID_CNT)
+ return;
+ psc_regs = davinci_psc0_regs;
+ mdstat = &psc_regs->psc0.mdstat[id];
+ mdctl = &psc_regs->psc0.mdctl[id];
+ } else {
+ id -= DAVINCI_LPSC_PSC1_BASE;
+ if (id >= PSC_PSC1_MODULE_ID_CNT)
+ return;
+ psc_regs = davinci_psc1_regs;
+ mdstat = &psc_regs->psc1.mdstat[id];
+ mdctl = &psc_regs->psc1.mdctl[id];
+ }
+ ptstat = &psc_regs->ptstat;
+ ptcmd = &psc_regs->ptcmd;
+#endif
- while (REG(PSC_PTSTAT) & 0x01)
+ while (readl(ptstat) & 0x01)
continue;
- if ((*mdstat & 0x1f) == 0x03)
- return; /* Already on and enabled */
+ if ((readl(mdstat) & 0x1f) == 0x03)
+ return; /* Already on and enabled */
- *mdctl |= 0x03;
+ writel(readl(mdctl) | 0x03, mdctl);
switch (id) {
#ifdef CONFIG_SOC_DM644X
case DAVINCI_LPSC_MEMSTICK:
case DAVINCI_LPSC_McBSP:
case DAVINCI_LPSC_GPIO:
- *mdctl |= 0x200;
+ writel(readl(mdctl) | 0x200, mdctl);
break;
#endif
}
- REG(PSC_PTCMD) = 0x01;
+ writel(0x01, ptcmd);
- while (REG(PSC_PTSTAT) & 0x03)
+ while (readl(ptstat) & 0x01)
continue;
- while ((*mdstat & 0x1f) != 0x03) /* Probably an overkill... */
+ while ((readl(mdstat) & 0x1f) != 0x03)
continue;
}
*/
#include <common.h>
+#include <asm/io.h>
-typedef volatile struct {
+struct davinci_timer {
u_int32_t pid12;
u_int32_t emumgt;
u_int32_t na1;
u_int32_t tcr;
u_int32_t tgcr;
u_int32_t wdtcr;
-} davinci_timer;
+};
-davinci_timer *timer = (davinci_timer *)CONFIG_SYS_TIMERBASE;
+static struct davinci_timer * const timer =
+ (struct davinci_timer *)CONFIG_SYS_TIMERBASE;
#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
#define TIM_CLK_DIV 16
int timer_init(void)
{
/* We are using timer34 in unchained 32-bit mode, full speed */
- timer->tcr = 0x0;
- timer->tgcr = 0x0;
- timer->tgcr = 0x06 | ((TIM_CLK_DIV - 1) << 8);
- timer->tim34 = 0x0;
- timer->prd34 = TIMER_LOAD_VAL;
+ writel(0x0, &timer->tcr);
+ writel(0x0, &timer->tgcr);
+ writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
+ writel(0x0, &timer->tim34);
+ writel(TIMER_LOAD_VAL, &timer->prd34);
lastinc = 0;
timestamp = 0;
- timer->tcr = 2 << 22;
+ writel(2 << 22, &timer->tcr);
return(0);
}
void reset_timer(void)
{
- timer->tcr = 0x0;
- timer->tim34 = 0;
+ writel(0x0, &timer->tcr);
+ writel(0x0, &timer->tim34);
lastinc = 0;
timestamp = 0;
- timer->tcr = 2 << 22;
+ writel(2 << 22, &timer->tcr);
}
static ulong get_timer_raw(void)
{
- ulong now = timer->tim34;
+ ulong now = readl(&timer->tim34);
if (now >= lastinc) {
/* normal mode */
writel(0, &sdrc_base->sysconfig);
/* setup sdrc to ball mux */
- writel(SDP_SDRC_SHARING, &sdrc_base->sharing);
+ writel(SDRC_SHARING, &sdrc_base->sharing);
/* Disable Power Down of CKE cuz of 1 CKE on combo part */
- writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
+ writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH,
+ &sdrc_base->power);
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
sdelay(0x20000);
****************************************************/
u32 is_mem_sdr(void)
{
- if (readl(&sdrc_base->cs[CS0].mr) == SDP_SDRC_MR_0_SDR)
+ if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
return 1;
return 0;
}
START-y += start.o
COBJS-y += cpu.o
-COBJS-y += hsdramc.o
+COBJS-$(CONFIG_SYS_HSDRAMC) += hsdramc.o
COBJS-y += exception.o
COBJS-y += cache.o
COBJS-y += interrupts.o
*/
#include <common.h>
-#ifdef CONFIG_SYS_HSDRAMC
#include <asm/io.h>
#include <asm/sdram.h>
return sdram_size;
}
-
-#endif /* CONFIG_SYS_HSDRAMC */
--- /dev/null
+Summary
+=======
+
+This README is about U-Boot support for TI's ARM 926EJS based family of SoCs.
+These SOCs are used for cameras, video security and surveillance, DVR's, etc.
+DaVinci SOC's comprise of DM644x, DM646x, DM35x and DM36x series of SOC's
+Additionally there are some SOCs meant for the audio market which though have
+an OMAP part number are very similar to the DaVinci series of SOC's
+Additionally, some family members contain a TI DSP and/or graphics
+co processors along with a host of other peripherals.
+
+Currently the following boards are supported:
+
+* TI DaVinci DM644x EVM
+
+* TI DaVinci DM646x EVM
+
+* TI DaVinci DM355 EVM
+
+* TI DaVinci DM365 EVM
+
+* TI DA830 EVM
+
+* DM355 based Leopard board
+
+* DM644x based schmoogie board
+
+* DM644x based sffsdr board
+
+* DM644x based sonata board
+
+Build
+=====
+
+* TI DaVinci DM644x EVM:
+
+make davinci_dvevm_config
+make
+
+* TI DaVinci DM646x EVM:
+
+make davinci_dm6467evm_config
+make
+
+* TI DaVinci DM355 EVM:
+
+make davinci_dm355evm_config
+make
+
+* TI DaVinci DM365 EVM:
+
+make davinci_dm365evm_config
+make
+
+* TI DA830 EVM:
+
+make da830evm_config
+make
+
+* DM355 based Leopard board:
+
+make davinci_dm355leopard_config
+make
+
+* DM644x based schmoogie board:
+
+make davinci_schmoogie_config
+make
+
+* DM644x based sffsdr board:
+
+make davinci_sffsdr_config
+make
+
+* DM644x based sonata board:
+
+make davinci_sonata_config
+make
+
+Bootloaders
+===============
+
+The DaVinci SOC's use 2 bootloaders. The low level initialization
+is done by a UBL(user boot loader). The UBL is written to a NAND/NOR/SPI flash
+by a programmer. During initial bootup, the ROM Bootloader reads the UBL
+from a storage device and loads it into the IRAM. The UBL then loads the U-Boot
+into the RAM.
+The programmers and UBL are always released as part of any standard TI
+software release associated with an SOC.
+
+Links
+=====
+
+1) TI DaVinci DM355 EVM:
+http://focus.ti.com/docs/prod/folders/print/tms320dm355.html
+http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=203&osCsid=c499af6087317f11b3da19b4e8f1af32
+
+2) TI DaVinci DM365 EVM:
+http://focus.ti.com/docs/prod/folders/print/tms320dm365.html?247SEM=
+http://support.spectrumdigital.com/boards/evmdm365/revc/
+
+3) DaVinci DM355 based leopard board
+http://designsomething.org/leopardboard/default.aspx
+http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=192&osCsid=67c20335668ffc57cb35727106eb24b1
+
+4) TI DaVinci DM6467 EVM:
+http://focus.ti.com/docs/prod/folders/print/tms320dm6467.html
+http://support.spectrumdigital.com/boards/evmdm6467/revf/
+
+5) TI DaVinci DM6446 EVM:
+http://focus.ti.com/docs/prod/folders/print/tms320dm6446.html
+http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=222
+
+6) TI DA830 EVM
+http://focus.ti.com/apps/docs/gencontent.tsp?appId=1&contentId=52385
+http://www.spectrumdigital.com/product_info.php?cPath=37&products_id=214
*/
#include <common.h>
-#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
-#endif
+#include <asm/arch/s3c24x0_cpu.h>
#include <asm/io.h>
#include <i2c.h>
{
t2_t *t2_base = (t2_t *)T2_BASE;
+#if defined(CONFIG_TWL4030_POWER)
twl4030_power_mmc_init();
+#endif
writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
#include <common.h>
#include <nand.h>
-#include <s3c2410.h>
+#include <asm/arch/s3c24x0_cpu.h>
#include <asm/io.h>
#define S3C2410_NFCONF_EN (1<<15)
#include <common.h>
#include <nand.h>
-#include <s3c6400.h>
+#include <asm/arch/s3c6400.h>
#include <asm/io.h>
#include <asm/errno.h>
COBJS-$(CONFIG_RTC_DS164x) += ds164x.o
COBJS-$(CONFIG_RTC_DS174x) += ds174x.o
COBJS-$(CONFIG_RTC_DS3231) += ds3231.o
+COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o
COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o
COBJS-$(CONFIG_RTC_M41T11) += m41t11.o
COBJS-$(CONFIG_RTC_M41T60) += m41t60.o
--- /dev/null
+/*
+ * Faraday FTRTC010 Real Time Clock
+ *
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <rtc.h>
+#include <asm/io.h>
+
+struct ftrtc010 {
+ unsigned int sec; /* 0x00 */
+ unsigned int min; /* 0x04 */
+ unsigned int hour; /* 0x08 */
+ unsigned int day; /* 0x0c */
+ unsigned int alarm_sec; /* 0x10 */
+ unsigned int alarm_min; /* 0x14 */
+ unsigned int alarm_hour; /* 0x18 */
+ unsigned int record; /* 0x1c */
+ unsigned int cr; /* 0x20 */
+};
+
+/*
+ * RTC Control Register
+ */
+#define FTRTC010_CR_ENABLE (1 << 0)
+#define FTRTC010_CR_INTERRUPT_SEC (1 << 1) /* per second irq */
+#define FTRTC010_CR_INTERRUPT_MIN (1 << 2) /* per minute irq */
+#define FTRTC010_CR_INTERRUPT_HR (1 << 3) /* per hour irq */
+#define FTRTC010_CR_INTERRUPT_DAY (1 << 4) /* per day irq */
+
+static struct ftrtc010 *rtc = (struct ftrtc010 *)CONFIG_FTRTC010_BASE;
+
+static void ftrtc010_enable(void)
+{
+ writel(FTRTC010_CR_ENABLE, &rtc->cr);
+}
+
+/*
+ * return current time in seconds
+ */
+static unsigned long ftrtc010_time(void)
+{
+ unsigned long day;
+ unsigned long hour;
+ unsigned long minute;
+ unsigned long second;
+ unsigned long second2;
+
+ do {
+ second = readl(&rtc->sec);
+ day = readl(&rtc->day);
+ hour = readl(&rtc->hour);
+ minute = readl(&rtc->min);
+ second2 = readl(&rtc->sec);
+ } while (second != second2);
+
+ return day * 24 * 60 * 60 + hour * 60 * 60 + minute * 60 + second;
+}
+
+/*
+ * Get the current time from the RTC
+ */
+
+int rtc_get(struct rtc_time *tmp)
+{
+ unsigned long now;
+
+ debug("%s(): record register: %x\n",
+ __func__, readl(&rtc->record));
+
+ now = ftrtc010_time() + readl(&rtc->record);
+
+ to_tm(now, tmp);
+
+ return 0;
+}
+
+/*
+ * Set the RTC
+ */
+int rtc_set(struct rtc_time *tmp)
+{
+ unsigned long new;
+ unsigned long now;
+
+ debug("%s(): DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ __func__,
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+ new = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour,
+ tmp->tm_min, tmp->tm_sec);
+
+ now = ftrtc010_time();
+
+ debug("%s(): write %lx to record register\n", __func__, new - now);
+
+ writel(new - now, &rtc->record);
+
+ return 0;
+}
+
+void rtc_reset(void)
+{
+ debug("%s()\n", __func__);
+ ftrtc010_enable();
+}
* Could not be tested as the reset pin is not wired on
* the sbc35-ag20 board
*/
- return 0;
}
#if (defined(CONFIG_CMD_DATE))
-#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
-#endif
+#include <asm/arch/s3c24x0_cpu.h>
#include <rtc.h>
#include <asm/io.h>
#include <common.h>
-#include <s3c6400.h>
+#include <asm/arch/s3c6400.h>
#ifdef CONFIG_SERIAL1
#define UART_NR S3C64XX_UART0
*/
#include <common.h>
-#if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB)
-#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
-#endif
+#include <asm/arch/s3c24x0_cpu.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
-static int serial_err_check(const int dev_index)
+static int serial_err_check(const int dev_index, int op)
{
struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index);
+ unsigned int mask;
+
+ /*
+ * UERSTAT
+ * Break Detect [3]
+ * Frame Err [2] : receive operation
+ * Parity Err [1] : receive operation
+ * Overrun Err [0] : receive operation
+ */
+ if (op)
+ mask = 0x8;
+ else
+ mask = 0xf;
- if (readl(&uart->uerstat) & 0xf)
- return 1;
-
- return 0;
+ return readl(&uart->uerstat) & mask;
}
/*
/* wait for character to arrive */
while (!(readl(&uart->utrstat) & 0x1)) {
- if (serial_err_check(dev_index))
+ if (serial_err_check(dev_index, 0))
return 0;
}
/* wait for room in the tx FIFO */
while (!(readl(&uart->utrstat) & 0x2)) {
- if (serial_err_check(dev_index))
+ if (serial_err_check(dev_index, 1))
return;
}
#endif
#if defined(CONFIG_ARM920T) || \
- defined(CONFIG_S3C2400) || \
- defined(CONFIG_S3C2410) || \
+ defined(CONFIG_S3C24X0) || \
defined(CONFIG_S3C6400) || \
defined(CONFIG_440EP) || \
defined(CONFIG_PCI_OHCI) || \
*/
#include <common.h>
-#include <s3c6400.h>
+#include <asm/arch/s3c6400.h>
int usb_cpu_init(void)
{
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __A320_H
+#define __A320_H
+
+/*
+ * Hardware register bases
+ */
+#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */
+#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */
+#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */
+#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */
+#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */
+#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */
+#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/
+
+#endif /* __A320_H */
+
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Power Management Unit
+ */
+#ifndef __FTPMU010_H
+#define __FTPMU010_H
+
+struct ftpmu010 {
+ unsigned int IDNMBR0; /* 0x00 */
+ unsigned int reserved0; /* 0x04 */
+ unsigned int OSCC; /* 0x08 */
+ unsigned int PMODE; /* 0x0C */
+ unsigned int PMCR; /* 0x10 */
+ unsigned int PED; /* 0x14 */
+ unsigned int PEDSR; /* 0x18 */
+ unsigned int reserved1; /* 0x1C */
+ unsigned int PMSR; /* 0x20 */
+ unsigned int PGSR; /* 0x24 */
+ unsigned int MFPSR; /* 0x28 */
+ unsigned int MISC; /* 0x2C */
+ unsigned int PDLLCR0; /* 0x30 */
+ unsigned int PDLLCR1; /* 0x34 */
+ unsigned int AHBMCLKOFF; /* 0x38 */
+ unsigned int APBMCLKOFF; /* 0x3C */
+ unsigned int DCSRCR0; /* 0x40 */
+ unsigned int DCSRCR1; /* 0x44 */
+ unsigned int DCSRCR2; /* 0x48 */
+ unsigned int SDRAMHTC; /* 0x4C */
+ unsigned int PSPR0; /* 0x50 */
+ unsigned int PSPR1; /* 0x54 */
+ unsigned int PSPR2; /* 0x58 */
+ unsigned int PSPR3; /* 0x5C */
+ unsigned int PSPR4; /* 0x60 */
+ unsigned int PSPR5; /* 0x64 */
+ unsigned int PSPR6; /* 0x68 */
+ unsigned int PSPR7; /* 0x6C */
+ unsigned int PSPR8; /* 0x70 */
+ unsigned int PSPR9; /* 0x74 */
+ unsigned int PSPR10; /* 0x78 */
+ unsigned int PSPR11; /* 0x7C */
+ unsigned int PSPR12; /* 0x80 */
+ unsigned int PSPR13; /* 0x84 */
+ unsigned int PSPR14; /* 0x88 */
+ unsigned int PSPR15; /* 0x8C */
+ unsigned int AHBDMA_RACCS; /* 0x90 */
+ unsigned int reserved2; /* 0x94 */
+ unsigned int reserved3; /* 0x98 */
+ unsigned int JSS; /* 0x9C */
+ unsigned int CFC_RACC; /* 0xA0 */
+ unsigned int SSP1_RACC; /* 0xA4 */
+ unsigned int UART1TX_RACC; /* 0xA8 */
+ unsigned int UART1RX_RACC; /* 0xAC */
+ unsigned int UART2TX_RACC; /* 0xB0 */
+ unsigned int UART2RX_RACC; /* 0xB4 */
+ unsigned int SDC_RACC; /* 0xB8 */
+ unsigned int I2SAC97_RACC; /* 0xBC */
+ unsigned int IRDATX_RACC; /* 0xC0 */
+ unsigned int reserved4; /* 0xC4 */
+ unsigned int USBD_RACC; /* 0xC8 */
+ unsigned int IRDARX_RACC; /* 0xCC */
+ unsigned int IRDA_RACC; /* 0xD0 */
+ unsigned int ED0_RACC; /* 0xD4 */
+ unsigned int ED1_RACC; /* 0xD8 */
+};
+
+/*
+ * ID Number 0 Register
+ */
+#define FTPMU010_ID_A320A 0x03200000
+#define FTPMU010_ID_A320C 0x03200010
+#define FTPMU010_ID_A320D 0x03200030
+
+/*
+ * OSC Control Register
+ */
+#define FTPMU010_OSCC_OSCH_TRI (1 << 11)
+#define FTPMU010_OSCC_OSCH_STABLE (1 << 9)
+#define FTPMU010_OSCC_OSCH_OFF (1 << 8)
+
+#define FTPMU010_OSCC_OSCL_TRI (1 << 3)
+#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2)
+#define FTPMU010_OSCC_OSCL_STABLE (1 << 1)
+#define FTPMU010_OSCC_OSCL_OFF (1 << 0)
+
+/*
+ * Power Mode Register
+ */
+#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7)
+#define FTPMU010_PMODE_FCS (1 << 2)
+#define FTPMU010_PMODE_TURBO (1 << 1)
+#define FTPMU010_PMODE_SLEEP (1 << 0)
+
+/*
+ * Power Manager Status Register
+ */
+#define FTPMU010_PMSR_SMR (1 << 10)
+
+#define FTPMU010_PMSR_RDH (1 << 2)
+#define FTPMU010_PMSR_PH (1 << 1)
+#define FTPMU010_PMSR_CKEHLOW (1 << 0)
+
+/*
+ * Multi-Function Port Setting Register
+ */
+#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14)
+#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13)
+#define FTPMU010_MFPSR_AC97PINSEL (1 << 3)
+
+/*
+ * PLL/DLL Control Register 0
+ */
+#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) >> 20) & 0xf)
+#define FTPMU010_PDLLCR0_DLLFRAG (1 << 19)
+#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18)
+#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17)
+#define FTPMU010_PDLLCR0_DLLDIS (1 << 16)
+#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) >> 3) & 0x1ff)
+#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2)
+#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1)
+#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0)
+
+#endif /* __FTPMU010_H */
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * SDRAM Controller
+ */
+#ifndef __FTSDMC020_H
+#define __FTSDMC020_H
+
+#define FTSDMC020_OFFSET_TP0 0x00
+#define FTSDMC020_OFFSET_TP1 0x04
+#define FTSDMC020_OFFSET_CR 0x08
+#define FTSDMC020_OFFSET_BANK0_BSR 0x0C
+#define FTSDMC020_OFFSET_BANK1_BSR 0x10
+#define FTSDMC020_OFFSET_BANK2_BSR 0x14
+#define FTSDMC020_OFFSET_BANK3_BSR 0x18
+#define FTSDMC020_OFFSET_BANK4_BSR 0x1C
+#define FTSDMC020_OFFSET_BANK5_BSR 0x20
+#define FTSDMC020_OFFSET_BANK6_BSR 0x24
+#define FTSDMC020_OFFSET_BANK7_BSR 0x28
+#define FTSDMC020_OFFSET_ACR 0x34
+
+/*
+ * Timing Parametet 0 Register
+ */
+#define FTSDMC020_TP0_TCL(x) ((x) & 0x3)
+#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4)
+#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8)
+#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12)
+#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16)
+#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20)
+
+/*
+ * Timing Parametet 1 Register
+ */
+#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff)
+#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16)
+#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20)
+
+/*
+ * Configuration Register
+ */
+#define FTSDMC020_CR_SREF (1 << 0)
+#define FTSDMC020_CR_PWDN (1 << 1)
+#define FTSDMC020_CR_ISMR (1 << 2)
+#define FTSDMC020_CR_IREF (1 << 3)
+#define FTSDMC020_CR_IPREC (1 << 4)
+#define FTSDMC020_CR_REFTYPE (1 << 5)
+
+/*
+ * SDRAM External Bank Base/Size Register
+ */
+#define FTSDMC020_BANK_ENABLE (1 << 28)
+
+#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16)
+
+#define FTSDMC020_BANK_DDW_X4 (0 << 12)
+#define FTSDMC020_BANK_DDW_X8 (1 << 12)
+#define FTSDMC020_BANK_DDW_X16 (2 << 12)
+#define FTSDMC020_BANK_DDW_X32 (3 << 12)
+
+#define FTSDMC020_BANK_DSZ_16M (0 << 8)
+#define FTSDMC020_BANK_DSZ_64M (1 << 8)
+#define FTSDMC020_BANK_DSZ_128M (2 << 8)
+#define FTSDMC020_BANK_DSZ_256M (3 << 8)
+
+#define FTSDMC020_BANK_MBW_8 (0 << 4)
+#define FTSDMC020_BANK_MBW_16 (1 << 4)
+#define FTSDMC020_BANK_MBW_32 (2 << 4)
+
+#define FTSDMC020_BANK_SIZE_1M 0x0
+#define FTSDMC020_BANK_SIZE_2M 0x1
+#define FTSDMC020_BANK_SIZE_4M 0x2
+#define FTSDMC020_BANK_SIZE_8M 0x3
+#define FTSDMC020_BANK_SIZE_16M 0x4
+#define FTSDMC020_BANK_SIZE_32M 0x5
+#define FTSDMC020_BANK_SIZE_64M 0x6
+#define FTSDMC020_BANK_SIZE_128M 0x7
+#define FTSDMC020_BANK_SIZE_256M 0x8
+
+/*
+ * Arbiter Control Register
+ */
+#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f)
+#define FTSDMC020_ACR_TOE (1 << 8)
+
+#endif /* __FTSDMC020_H */
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Static Memory Controller
+ */
+#ifndef __FTSMC020_H
+#define __FTSMC020_H
+
+#ifndef __ASSEMBLY__
+
+struct ftsmc020 {
+ struct {
+ unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */
+ unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */
+ } bank[4];
+ unsigned int pad[8]; /* 0x20 - 0x3c */
+ unsigned int ssr; /* 0x40 */
+};
+
+void ftsmc020_init(void);
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Memory Bank Configuration Register
+ */
+#define FTSMC020_BANK_ENABLE (1 << 28)
+#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000)
+
+#define FTSMC020_BANK_WPROT (1 << 11)
+
+#define FTSMC020_BANK_SIZE_32K (0xb << 4)
+#define FTSMC020_BANK_SIZE_64K (0xc << 4)
+#define FTSMC020_BANK_SIZE_128K (0xd << 4)
+#define FTSMC020_BANK_SIZE_256K (0xe << 4)
+#define FTSMC020_BANK_SIZE_512K (0xf << 4)
+#define FTSMC020_BANK_SIZE_1M (0x0 << 4)
+#define FTSMC020_BANK_SIZE_2M (0x1 << 4)
+#define FTSMC020_BANK_SIZE_4M (0x2 << 4)
+#define FTSMC020_BANK_SIZE_8M (0x3 << 4)
+#define FTSMC020_BANK_SIZE_16M (0x4 << 4)
+#define FTSMC020_BANK_SIZE_32M (0x5 << 4)
+
+#define FTSMC020_BANK_MBW_8 (0x0 << 0)
+#define FTSMC020_BANK_MBW_16 (0x1 << 0)
+#define FTSMC020_BANK_MBW_32 (0x2 << 0)
+
+/*
+ * Memory Bank Timing Parameter Register
+ */
+#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28)
+#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24)
+#define FTSMC020_TPR_RBE (1 << 20)
+#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18)
+#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16)
+#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12)
+#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8)
+#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6)
+#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4)
+#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0)
+
+#endif /* __FTSMC020_H */
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Timer
+ */
+#ifndef __FTTMR010_H
+#define __FTTMR010_H
+
+struct fttmr010 {
+ unsigned int timer1_counter; /* 0x00 */
+ unsigned int timer1_load; /* 0x04 */
+ unsigned int timer1_match1; /* 0x08 */
+ unsigned int timer1_match2; /* 0x0c */
+ unsigned int timer2_counter; /* 0x10 */
+ unsigned int timer2_load; /* 0x14 */
+ unsigned int timer2_match1; /* 0x18 */
+ unsigned int timer2_match2; /* 0x1c */
+ unsigned int timer3_counter; /* 0x20 */
+ unsigned int timer3_load; /* 0x24 */
+ unsigned int timer3_match1; /* 0x28 */
+ unsigned int timer3_match2; /* 0x2c */
+ unsigned int cr; /* 0x30 */
+ unsigned int interrupt_state; /* 0x34 */
+ unsigned int interrupt_mask; /* 0x38 */
+};
+
+/*
+ * Timer Control Register
+ */
+#define FTTMR010_TM3_UPDOWN (1 << 11)
+#define FTTMR010_TM2_UPDOWN (1 << 10)
+#define FTTMR010_TM1_UPDOWN (1 << 9)
+#define FTTMR010_TM3_OFENABLE (1 << 8)
+#define FTTMR010_TM3_CLOCK (1 << 7)
+#define FTTMR010_TM3_ENABLE (1 << 6)
+#define FTTMR010_TM2_OFENABLE (1 << 5)
+#define FTTMR010_TM2_CLOCK (1 << 4)
+#define FTTMR010_TM2_ENABLE (1 << 3)
+#define FTTMR010_TM1_OFENABLE (1 << 2)
+#define FTTMR010_TM1_CLOCK (1 << 1)
+#define FTTMR010_TM1_ENABLE (1 << 0)
+
+/*
+ * Timer Interrupt State & Mask Registers
+ */
+#define FTTMR010_TM3_OVERFLOW (1 << 8)
+#define FTTMR010_TM3_MATCH2 (1 << 7)
+#define FTTMR010_TM3_MATCH1 (1 << 6)
+#define FTTMR010_TM2_OVERFLOW (1 << 5)
+#define FTTMR010_TM2_MATCH2 (1 << 4)
+#define FTTMR010_TM2_MATCH1 (1 << 3)
+#define FTTMR010_TM1_OVERFLOW (1 << 2)
+#define FTTMR010_TM1_MATCH2 (1 << 1)
+#define FTTMR010_TM1_MATCH1 (1 << 0)
+
+#endif /* __FTTMR010_H */
* on other DaVinci chips. Double check them before you try
* using the addresses ... or PSC module identifiers, etc.
*/
+#ifndef CONFIG_SOC_DA8XX
+
#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
#endif
+#else /* CONFIG_SOC_DA8XX */
+
+#define DAVINCI_UART0_BASE 0x01c42000
+#define DAVINCI_UART1_BASE 0x01d0c000
+#define DAVINCI_UART2_BASE 0x01d0d000
+#define DAVINCI_I2C0_BASE 0x01c22000
+#define DAVINCI_I2C1_BASE 0x01e28000
+#define DAVINCI_TIMER0_BASE 0x01c20000
+#define DAVINCI_TIMER1_BASE 0x01c21000
+#define DAVINCI_WDOG_BASE 0x01c21000
+#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
+#define DAVINCI_PSC0_BASE 0x01c10000
+#define DAVINCI_PSC1_BASE 0x01e27000
+#define DAVINCI_SPI0_BASE 0x01c41000
+#define DAVINCI_USB_OTG_BASE 0x01e00000
+#define DAVINCI_SPI1_BASE 0x01e12000
+#define DAVINCI_GPIO_BASE 0x01e26000
+#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
+#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
+#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
+#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
+#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
+#define DAVINCI_INTC_BASE 0xfffee000
+#define DAVINCI_BOOTCFG_BASE 0x01c14000
+
+#endif /* CONFIG_SOC_DA8XX */
+
/* Power and Sleep Controller (PSC) Domains */
#define DAVINCI_GPSC_ARMDOMAIN 0
#define DAVINCI_GPSC_DSPDOMAIN 1
+#ifndef CONFIG_SOC_DA8XX
+
#define DAVINCI_LPSC_VPSSMSTR 0
#define DAVINCI_LPSC_VPSSSLV 1
#define DAVINCI_LPSC_TPCC 2
#define DAVINCI_DM646X_LPSC_UART0 26
#define DAVINCI_DM646X_LPSC_I2C 31
+#else /* CONFIG_SOC_DA8XX */
+
+enum davinci_lpsc_ids {
+ DAVINCI_LPSC_TPCC = 0,
+ DAVINCI_LPSC_TPTC0,
+ DAVINCI_LPSC_TPTC1,
+ DAVINCI_LPSC_AEMIF,
+ DAVINCI_LPSC_SPI0,
+ DAVINCI_LPSC_MMC_SD,
+ DAVINCI_LPSC_AINTC,
+ DAVINCI_LPSC_ARM_RAM_ROM,
+ DAVINCI_LPSC_SECCTL_KEYMGR,
+ DAVINCI_LPSC_UART0,
+ DAVINCI_LPSC_SCR0,
+ DAVINCI_LPSC_SCR1,
+ DAVINCI_LPSC_SCR2,
+ DAVINCI_LPSC_DMAX,
+ DAVINCI_LPSC_ARM,
+ DAVINCI_LPSC_GEM,
+ /* for LPSCs in PSC1, offset from 32 for differentiation */
+ DAVINCI_LPSC_PSC1_BASE = 32,
+ DAVINCI_LPSC_USB11,
+ DAVINCI_LPSC_USB20,
+ DAVINCI_LPSC_GPIO,
+ DAVINCI_LPSC_UHPI,
+ DAVINCI_LPSC_EMAC,
+ DAVINCI_LPSC_DDR_EMIF,
+ DAVINCI_LPSC_McASP0,
+ DAVINCI_LPSC_McASP1,
+ DAVINCI_LPSC_McASP2,
+ DAVINCI_LPSC_SPI1,
+ DAVINCI_LPSC_I2C1,
+ DAVINCI_LPSC_UART1,
+ DAVINCI_LPSC_UART2,
+ DAVINCI_LPSC_LCDC,
+ DAVINCI_LPSC_ePWM,
+ DAVINCI_LPSC_eCAP,
+ DAVINCI_LPSC_eQEP,
+ DAVINCI_LPSC_SCR_P0,
+ DAVINCI_LPSC_SCR_P1,
+ DAVINCI_LPSC_CR_P3,
+ DAVINCI_LPSC_L3_CBA_RAM
+};
+
+#endif /* CONFIG_SOC_DA8XX */
+
void lpsc_on(unsigned int id);
void dsp_on(void);
void davinci_enable_i2c(void);
void davinci_errata_workarounds(void);
+#ifndef CONFIG_SOC_DA8XX
+
/* Some PSC defines */
#define PSC_CHP_SHRTSW (0x01c40038)
#define PSC_GBLCTL (0x01c41010)
#define PSC_SILVER_BULLET (0x01c41a20)
+#else /* CONFIG_SOC_DA8XX */
+
+#define PSC_PSC0_MODULE_ID_CNT 16
+#define PSC_PSC1_MODULE_ID_CNT 32
+
+struct davinci_psc_regs {
+ dv_reg revid;
+ dv_reg rsvd0[71];
+ dv_reg ptcmd;
+ dv_reg rsvd1;
+ dv_reg ptstat;
+ dv_reg rsvd2[437];
+ union {
+ struct {
+ dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];
+ dv_reg rsvd3[112];
+ dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];
+ } psc0;
+ struct {
+ dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT];
+ dv_reg rsvd3[96];
+ dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT];
+ } psc1;
+ };
+};
+
+#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
+#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
+
+#endif /* CONFIG_SOC_DA8XX */
+
+#ifndef CONFIG_SOC_DA8XX
+
/* Miscellania... */
#define VBPR (0x20000020)
#define PINMUX3 0x01c4000c
#define PINMUX4 0x01c40010
+#else /* CONFIG_SOC_DA8XX */
+
+struct davinci_pllc_regs {
+ dv_reg revid;
+ dv_reg rsvd1[56];
+ dv_reg rstype;
+ dv_reg rsvd2[6];
+ dv_reg pllctl;
+ dv_reg ocsel;
+ dv_reg rsvd3[2];
+ dv_reg pllm;
+ dv_reg prediv;
+ dv_reg plldiv1;
+ dv_reg plldiv2;
+ dv_reg plldiv3;
+ dv_reg oscdiv;
+ dv_reg postdiv;
+ dv_reg rsvd4[3];
+ dv_reg pllcmd;
+ dv_reg pllstat;
+ dv_reg alnctl;
+ dv_reg dchange;
+ dv_reg cken;
+ dv_reg ckstat;
+ dv_reg systat;
+ dv_reg rsvd5[3];
+ dv_reg plldiv4;
+ dv_reg plldiv5;
+ dv_reg plldiv6;
+ dv_reg plldiv7;
+ dv_reg rsvd6[32];
+ dv_reg emucnt0;
+ dv_reg emucnt1;
+};
+
+#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define DAVINCI_PLLC_DIV_MASK 0x1f
+
+/* Clock IDs */
+enum davinci_clk_ids {
+ DAVINCI_SPI0_CLKID = 2,
+ DAVINCI_UART2_CLKID = 2,
+ DAVINCI_MDIO_CLKID = 4,
+ DAVINCI_ARM_CLKID = 6,
+ DAVINCI_PLLM_CLKID = 0xff,
+ DAVINCI_PLLC_CLKID = 0x100,
+ DAVINCI_AUXCLK_CLKID = 0x101
+};
+
+int clk_get(enum davinci_clk_ids id);
+
+/* Boot config */
+struct davinci_syscfg_regs {
+ dv_reg revid;
+ dv_reg rsvd[71];
+ dv_reg pinmux[20];
+ dv_reg suspsrc;
+ dv_reg chipsig;
+ dv_reg chipsig_clr;
+ dv_reg cfgchip0;
+ dv_reg cfgchip1;
+ dv_reg cfgchip2;
+ dv_reg cfgchip3;
+ dv_reg cfgchip4;
+};
+
+#define davinci_syscfg_regs \
+ ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
+
+/* Emulation suspend bits */
+#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
+#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
+#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
+#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
+#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
+
+/* Interrupt controller */
+struct davinci_aintc_regs {
+ dv_reg revid;
+ dv_reg cr;
+ dv_reg dummy0[2];
+ dv_reg ger;
+ dv_reg dummy1[219];
+ dv_reg ecr1;
+ dv_reg ecr2;
+ dv_reg ecr3;
+ dv_reg dummy2[1117];
+ dv_reg hier;
+};
+
+#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
+
+struct davinci_uart_ctrl_regs {
+ dv_reg revid1;
+ dv_reg revid2;
+ dv_reg pwremu_mgmt;
+ dv_reg mdr;
+};
+
+#define DAVINCI_UART_CTRL_BASE 0x28
+#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
+#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
+#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
+
+#define davinci_uart0_ctrl_regs \
+ ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
+#define davinci_uart1_ctrl_regs \
+ ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
+#define davinci_uart2_ctrl_regs \
+ ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
+
+/* UART PWREMU_MGMT definitions */
+#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
+#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
+#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
+
+#endif /* CONFIG_SOC_DA8XX */
+
#endif /* __ASM_ARCH_HARDWARE_H */
#define I2C_WRITE 0
#define I2C_READ 1
+#ifndef CONFIG_SOC_DA8XX
#define I2C_BASE 0x01c21000
+#else
+#define I2C_BASE 0x01c22000
+#endif
#define I2C_OA (I2C_BASE + 0x00)
#define I2C_IE (I2C_BASE + 0x04)
#define I2C_CON_XA (1 << 8) /* Expand address */
#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
+#define I2C_CON_FREE (1 << 14) /* Free run on emulation */
#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */
#define PAGEPOLICY_HIGH (0x1 << 0)
#define SRFRONRESET (0x1 << 7)
+#define PWDNEN (0x1 << 2)
#define WAKEUPPROC (0x1 << 26)
#define DDR_SDRAM (0x1 << 0)
#define EARLY_INIT 1
/* Slower full frequency range default timings for x32 operation*/
-#define SDP_SDRC_SHARING 0x00000100
-#define SDP_SDRC_MR_0_SDR 0x00000031
-
-/* optimized timings good for current shipping parts */
-#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
+#define SDRC_SHARING 0x00000100
+#define SDRC_MR_0_SDR 0x00000031
#define DLL_OFFSET 0
#define DLL_WRITEDDRCLKX2DIS 1
* TCKE = 2
* XSR = 120/6 = 20
*/
-#define TDAL_165 6
-#define TDPL_165 3
-#define TRRD_165 2
-#define TRCD_165 3
-#define TRP_165 3
-#define TRAS_165 7
-#define TRC_165 10
-#define TRFC_165 21
-#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \
- (TRAS_165 << 18) | (TRP_165 << 15) | \
- (TRCD_165 << 12) | (TRRD_165 << 9) | \
- (TDPL_165 << 6) | (TDAL_165))
-
-#define TWTR_165 1
-#define TCKE_165 1
-#define TXP_165 5
-#define XSR_165 23
-#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \
- (TXP_165 << 8) | (TWTR_165 << 16))
-
-#define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
-#define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165
-#define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
+#define INFINEON_TDAL_165 6
+#define INFINEON_TDPL_165 3
+#define INFINEON_TRRD_165 2
+#define INFINEON_TRCD_165 3
+#define INFINEON_TRP_165 3
+#define INFINEON_TRAS_165 7
+#define INFINEON_TRC_165 10
+#define INFINEON_TRFC_165 12
+#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | \
+ (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) | \
+ (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) | \
+ (INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) | \
+ (INFINEON_TDAL_165))
+
+#define INFINEON_TWTR_165 1
+#define INFINEON_TCKE_165 2
+#define INFINEON_TXP_165 2
+#define INFINEON_XSR_165 20
+#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | \
+ (INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) | \
+ (INFINEON_TWTR_165 << 16))
+
+/* Micron part of 3430 EVM (165MHz optimized) 6.06ns
+ * ACTIMA
+ * TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6
+ * TDPL (Twr) = 15/6 = 2.5 -> 3
+ * TRRD = 12/6 = 2
+ * TRCD = 18/6 = 3
+ * TRP = 18/6 = 3
+ * TRAS = 42/6 = 7
+ * TRC = 60/6 = 10
+ * TRFC = 125/6 = 21
+ * ACTIMB
+ * TWTR = 1
+ * TCKE = 1
+ * TXSR = 138/6 = 23
+ * TXP = 25/6 = 4.1 ~5
+ */
+#define MICRON_TDAL_165 6
+#define MICRON_TDPL_165 3
+#define MICRON_TRRD_165 2
+#define MICRON_TRCD_165 3
+#define MICRON_TRP_165 3
+#define MICRON_TRAS_165 7
+#define MICRON_TRC_165 10
+#define MICRON_TRFC_165 21
+#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | \
+ (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) | \
+ (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) | \
+ (MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) | \
+ (MICRON_TDAL_165))
+
+#define MICRON_TWTR_165 1
+#define MICRON_TCKE_165 1
+#define MICRON_XSR_165 23
+#define MICRON_TXP_165 5
+#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | \
+ (MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \
+ (MICRON_TWTR_165 << 16))
+
+#ifdef CONFIG_OMAP3_INFINEON_DDR
+#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
+#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
+#endif
+#ifdef CONFIG_OMAP3_MICRON_DDR
+#define V_ACTIMA_165 MICRON_V_ACTIMA_165
+#define V_ACTIMB_165 MICRON_V_ACTIMB_165
+#endif
+
+#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
+#error "Please choose the right DDR type in config header"
+#endif
/*
* GPMC settings -
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME : s3c2400.h
+ * Version : 31.3.2003
+ *
+ * Based on S3C2400X User's manual Rev 1.1
+ ************************************************/
+
+#ifndef __S3C2400_H__
+#define __S3C2400_H__
+
+#define S3C24X0_UART_CHANNELS 2
+#define S3C24X0_SPI_CHANNELS 1
+#define PALETTE (0x14A00400) /* SJS */
+
+enum s3c24x0_uarts_nr {
+ S3C24X0_UART0,
+ S3C24X0_UART1,
+};
+
+/*S3C2400 device base addresses */
+#define S3C24X0_MEMCTL_BASE 0x14000000
+#define S3C24X0_USB_HOST_BASE 0x14200000
+#define S3C24X0_INTERRUPT_BASE 0x14400000
+#define S3C24X0_DMA_BASE 0x14600000
+#define S3C24X0_CLOCK_POWER_BASE 0x14800000
+#define S3C24X0_LCD_BASE 0x14A00000
+#define S3C24X0_UART_BASE 0x15000000
+#define S3C24X0_TIMER_BASE 0x15100000
+#define S3C24X0_USB_DEVICE_BASE 0x15200140
+#define S3C24X0_WATCHDOG_BASE 0x15300000
+#define S3C24X0_I2C_BASE 0x15400000
+#define S3C24X0_I2S_BASE 0x15508000
+#define S3C24X0_GPIO_BASE 0x15600000
+#define S3C24X0_RTC_BASE 0x15700000
+#define S3C24X0_ADC_BASE 0x15800000
+#define S3C24X0_SPI_BASE 0x15900000
+#define S3C2400_MMC_BASE 0x15A00000
+
+/* include common stuff */
+#include <asm/arch/s3c24x0.h>
+
+
+static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
+{
+ return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
+}
+
+static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
+{
+ return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
+}
+
+static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
+{
+ return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
+}
+
+static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
+{
+ return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
+}
+
+static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
+{
+ return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
+}
+
+static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
+{
+ return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
+}
+
+static inline struct s3c24x0_uart
+ *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
+{
+ return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
+}
+
+static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
+{
+ return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
+}
+
+static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
+{
+ return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
+}
+
+static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
+{
+ return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
+}
+
+static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
+{
+ return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
+}
+
+static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
+{
+ return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
+}
+
+static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
+{
+ return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
+}
+
+static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
+{
+ return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
+}
+
+static inline struct s3c2400_adc *s3c2400_get_base_adc(void)
+{
+ return (struct s3c2400_adc *)S3C24X0_ADC_BASE;
+}
+
+static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
+{
+ return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
+}
+
+static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void)
+{
+ return (struct s3c2400_mmc *)S3C2400_MMC_BASE;
+}
+
+#endif /*__S3C2400_H__*/
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME : s3c2410.h
+ * Version : 31.3.2003
+ *
+ * Based on S3C2410X User's manual Rev 1.1
+ ************************************************/
+
+#ifndef __S3C2410_H__
+#define __S3C2410_H__
+
+#define S3C24X0_UART_CHANNELS 3
+#define S3C24X0_SPI_CHANNELS 2
+
+/* S3C2410 only supports 512 Byte HW ECC */
+#define S3C2410_ECCSIZE 512
+#define S3C2410_ECCBYTES 3
+
+enum s3c24x0_uarts_nr {
+ S3C24X0_UART0,
+ S3C24X0_UART1,
+ S3C24X0_UART2
+};
+
+/* S3C2410 device base addresses */
+#define S3C24X0_MEMCTL_BASE 0x48000000
+#define S3C24X0_USB_HOST_BASE 0x49000000
+#define S3C24X0_INTERRUPT_BASE 0x4A000000
+#define S3C24X0_DMA_BASE 0x4B000000
+#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
+#define S3C24X0_LCD_BASE 0x4D000000
+#define S3C2410_NAND_BASE 0x4E000000
+#define S3C24X0_UART_BASE 0x50000000
+#define S3C24X0_TIMER_BASE 0x51000000
+#define S3C24X0_USB_DEVICE_BASE 0x52000140
+#define S3C24X0_WATCHDOG_BASE 0x53000000
+#define S3C24X0_I2C_BASE 0x54000000
+#define S3C24X0_I2S_BASE 0x55000000
+#define S3C24X0_GPIO_BASE 0x56000000
+#define S3C24X0_RTC_BASE 0x57000000
+#define S3C2410_ADC_BASE 0x58000000
+#define S3C24X0_SPI_BASE 0x59000000
+#define S3C2410_SDI_BASE 0x5A000000
+
+
+/* include common stuff */
+#include <asm/arch/s3c24x0.h>
+
+
+static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
+{
+ return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
+}
+
+static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
+{
+ return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
+}
+
+static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
+{
+ return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
+}
+
+static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
+{
+ return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
+}
+
+static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
+{
+ return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
+}
+
+static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
+{
+ return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
+}
+
+static inline struct s3c2410_nand *s3c2410_get_base_nand(void)
+{
+ return (struct s3c2410_nand *)S3C2410_NAND_BASE;
+}
+
+static inline struct s3c24x0_uart
+ *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
+{
+ return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
+}
+
+static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
+{
+ return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
+}
+
+static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
+{
+ return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
+}
+
+static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
+{
+ return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
+}
+
+static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
+{
+ return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
+}
+
+static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
+{
+ return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
+}
+
+static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
+{
+ return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
+}
+
+static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
+{
+ return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
+}
+
+static inline struct s3c2410_adc *s3c2410_get_base_adc(void)
+{
+ return (struct s3c2410_adc *)S3C2410_ADC_BASE;
+}
+
+static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
+{
+ return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
+}
+
+static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void)
+{
+ return (struct s3c2410_sdi *)S3C2410_SDI_BASE;
+}
+
+#endif /*__S3C2410_H__*/
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME : s3c24x0.h
+ * Version : 31.3.2003
+ *
+ * common stuff for SAMSUNG S3C24X0 SoC
+ ************************************************/
+
+#ifndef __S3C24X0_H__
+#define __S3C24X0_H__
+
+/* Memory controller (see manual chapter 5) */
+struct s3c24x0_memctl {
+ u32 BWSCON;
+ u32 BANKCON[8];
+ u32 REFRESH;
+ u32 BANKSIZE;
+ u32 MRSRB6;
+ u32 MRSRB7;
+};
+
+
+/* USB HOST (see manual chapter 12) */
+struct s3c24x0_usb_host {
+ u32 HcRevision;
+ u32 HcControl;
+ u32 HcCommonStatus;
+ u32 HcInterruptStatus;
+ u32 HcInterruptEnable;
+ u32 HcInterruptDisable;
+ u32 HcHCCA;
+ u32 HcPeriodCuttendED;
+ u32 HcControlHeadED;
+ u32 HcControlCurrentED;
+ u32 HcBulkHeadED;
+ u32 HcBuldCurrentED;
+ u32 HcDoneHead;
+ u32 HcRmInterval;
+ u32 HcFmRemaining;
+ u32 HcFmNumber;
+ u32 HcPeriodicStart;
+ u32 HcLSThreshold;
+ u32 HcRhDescriptorA;
+ u32 HcRhDescriptorB;
+ u32 HcRhStatus;
+ u32 HcRhPortStatus1;
+ u32 HcRhPortStatus2;
+};
+
+
+/* INTERRUPT (see manual chapter 14) */
+struct s3c24x0_interrupt {
+ u32 SRCPND;
+ u32 INTMOD;
+ u32 INTMSK;
+ u32 PRIORITY;
+ u32 INTPND;
+ u32 INTOFFSET;
+#ifdef CONFIG_S3C2410
+ u32 SUBSRCPND;
+ u32 INTSUBMSK;
+#endif
+};
+
+
+/* DMAS (see manual chapter 8) */
+struct s3c24x0_dma {
+ u32 DISRC;
+#ifdef CONFIG_S3C2410
+ u32 DISRCC;
+#endif
+ u32 DIDST;
+#ifdef CONFIG_S3C2410
+ u32 DIDSTC;
+#endif
+ u32 DCON;
+ u32 DSTAT;
+ u32 DCSRC;
+ u32 DCDST;
+ u32 DMASKTRIG;
+#ifdef CONFIG_S3C2400
+ u32 res[1];
+#endif
+#ifdef CONFIG_S3C2410
+ u32 res[7];
+#endif
+};
+
+struct s3c24x0_dmas {
+ struct s3c24x0_dma dma[4];
+};
+
+
+/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
+/* (see S3C2410 manual chapter 7) */
+struct s3c24x0_clock_power {
+ u32 LOCKTIME;
+ u32 MPLLCON;
+ u32 UPLLCON;
+ u32 CLKCON;
+ u32 CLKSLOW;
+ u32 CLKDIVN;
+};
+
+
+/* LCD CONTROLLER (see manual chapter 15) */
+struct s3c24x0_lcd {
+ u32 LCDCON1;
+ u32 LCDCON2;
+ u32 LCDCON3;
+ u32 LCDCON4;
+ u32 LCDCON5;
+ u32 LCDSADDR1;
+ u32 LCDSADDR2;
+ u32 LCDSADDR3;
+ u32 REDLUT;
+ u32 GREENLUT;
+ u32 BLUELUT;
+ u32 res[8];
+ u32 DITHMODE;
+ u32 TPAL;
+#ifdef CONFIG_S3C2410
+ u32 LCDINTPND;
+ u32 LCDSRCPND;
+ u32 LCDINTMSK;
+ u32 LPCSEL;
+#endif
+};
+
+
+/* NAND FLASH (see S3C2410 manual chapter 6) */
+struct s3c2410_nand {
+ u32 NFCONF;
+ u32 NFCMD;
+ u32 NFADDR;
+ u32 NFDATA;
+ u32 NFSTAT;
+ u32 NFECC;
+};
+
+
+/* UART (see manual chapter 11) */
+struct s3c24x0_uart {
+ u32 ULCON;
+ u32 UCON;
+ u32 UFCON;
+ u32 UMCON;
+ u32 UTRSTAT;
+ u32 UERSTAT;
+ u32 UFSTAT;
+ u32 UMSTAT;
+#ifdef __BIG_ENDIAN
+ u8 res1[3];
+ u8 UTXH;
+ u8 res2[3];
+ u8 URXH;
+#else /* Little Endian */
+ u8 UTXH;
+ u8 res1[3];
+ u8 URXH;
+ u8 res2[3];
+#endif
+ u32 UBRDIV;
+};
+
+
+/* PWM TIMER (see manual chapter 10) */
+struct s3c24x0_timer {
+ u32 TCNTB;
+ u32 TCMPB;
+ u32 TCNTO;
+};
+
+struct s3c24x0_timers {
+ u32 TCFG0;
+ u32 TCFG1;
+ u32 TCON;
+ struct s3c24x0_timer ch[4];
+ u32 TCNTB4;
+ u32 TCNTO4;
+};
+
+
+/* USB DEVICE (see manual chapter 13) */
+struct s3c24x0_usb_dev_fifos {
+#ifdef __BIG_ENDIAN
+ u8 res[3];
+ u8 EP_FIFO_REG;
+#else /* little endian */
+ u8 EP_FIFO_REG;
+ u8 res[3];
+#endif
+};
+
+struct s3c24x0_usb_dev_dmas {
+#ifdef __BIG_ENDIAN
+ u8 res1[3];
+ u8 EP_DMA_CON;
+ u8 res2[3];
+ u8 EP_DMA_UNIT;
+ u8 res3[3];
+ u8 EP_DMA_FIFO;
+ u8 res4[3];
+ u8 EP_DMA_TTC_L;
+ u8 res5[3];
+ u8 EP_DMA_TTC_M;
+ u8 res6[3];
+ u8 EP_DMA_TTC_H;
+#else /* little endian */
+ u8 EP_DMA_CON;
+ u8 res1[3];
+ u8 EP_DMA_UNIT;
+ u8 res2[3];
+ u8 EP_DMA_FIFO;
+ u8 res3[3];
+ u8 EP_DMA_TTC_L;
+ u8 res4[3];
+ u8 EP_DMA_TTC_M;
+ u8 res5[3];
+ u8 EP_DMA_TTC_H;
+ u8 res6[3];
+#endif
+};
+
+struct s3c24x0_usb_device {
+#ifdef __BIG_ENDIAN
+ u8 res1[3];
+ u8 FUNC_ADDR_REG;
+ u8 res2[3];
+ u8 PWR_REG;
+ u8 res3[3];
+ u8 EP_INT_REG;
+ u8 res4[15];
+ u8 USB_INT_REG;
+ u8 res5[3];
+ u8 EP_INT_EN_REG;
+ u8 res6[15];
+ u8 USB_INT_EN_REG;
+ u8 res7[3];
+ u8 FRAME_NUM1_REG;
+ u8 res8[3];
+ u8 FRAME_NUM2_REG;
+ u8 res9[3];
+ u8 INDEX_REG;
+ u8 res10[7];
+ u8 MAXP_REG;
+ u8 res11[3];
+ u8 EP0_CSR_IN_CSR1_REG;
+ u8 res12[3];
+ u8 IN_CSR2_REG;
+ u8 res13[7];
+ u8 OUT_CSR1_REG;
+ u8 res14[3];
+ u8 OUT_CSR2_REG;
+ u8 res15[3];
+ u8 OUT_FIFO_CNT1_REG;
+ u8 res16[3];
+ u8 OUT_FIFO_CNT2_REG;
+#else /* little endian */
+ u8 FUNC_ADDR_REG;
+ u8 res1[3];
+ u8 PWR_REG;
+ u8 res2[3];
+ u8 EP_INT_REG;
+ u8 res3[15];
+ u8 USB_INT_REG;
+ u8 res4[3];
+ u8 EP_INT_EN_REG;
+ u8 res5[15];
+ u8 USB_INT_EN_REG;
+ u8 res6[3];
+ u8 FRAME_NUM1_REG;
+ u8 res7[3];
+ u8 FRAME_NUM2_REG;
+ u8 res8[3];
+ u8 INDEX_REG;
+ u8 res9[7];
+ u8 MAXP_REG;
+ u8 res10[7];
+ u8 EP0_CSR_IN_CSR1_REG;
+ u8 res11[3];
+ u8 IN_CSR2_REG;
+ u8 res12[3];
+ u8 OUT_CSR1_REG;
+ u8 res13[7];
+ u8 OUT_CSR2_REG;
+ u8 res14[3];
+ u8 OUT_FIFO_CNT1_REG;
+ u8 res15[3];
+ u8 OUT_FIFO_CNT2_REG;
+ u8 res16[3];
+#endif /* __BIG_ENDIAN */
+ struct s3c24x0_usb_dev_fifos fifo[5];
+ struct s3c24x0_usb_dev_dmas dma[5];
+};
+
+
+/* WATCH DOG TIMER (see manual chapter 18) */
+struct s3c24x0_watchdog {
+ u32 WTCON;
+ u32 WTDAT;
+ u32 WTCNT;
+};
+
+
+/* IIC (see manual chapter 20) */
+struct s3c24x0_i2c {
+ u32 IICCON;
+ u32 IICSTAT;
+ u32 IICADD;
+ u32 IICDS;
+};
+
+
+/* IIS (see manual chapter 21) */
+struct s3c24x0_i2s {
+#ifdef __BIG_ENDIAN
+ u16 res1;
+ u16 IISCON;
+ u16 res2;
+ u16 IISMOD;
+ u16 res3;
+ u16 IISPSR;
+ u16 res4;
+ u16 IISFCON;
+ u16 res5;
+ u16 IISFIFO;
+#else /* little endian */
+ u16 IISCON;
+ u16 res1;
+ u16 IISMOD;
+ u16 res2;
+ u16 IISPSR;
+ u16 res3;
+ u16 IISFCON;
+ u16 res4;
+ u16 IISFIFO;
+ u16 res5;
+#endif
+};
+
+
+/* I/O PORT (see manual chapter 9) */
+struct s3c24x0_gpio {
+#ifdef CONFIG_S3C2400
+ u32 PACON;
+ u32 PADAT;
+
+ u32 PBCON;
+ u32 PBDAT;
+ u32 PBUP;
+
+ u32 PCCON;
+ u32 PCDAT;
+ u32 PCUP;
+
+ u32 PDCON;
+ u32 PDDAT;
+ u32 PDUP;
+
+ u32 PECON;
+ u32 PEDAT;
+ u32 PEUP;
+
+ u32 PFCON;
+ u32 PFDAT;
+ u32 PFUP;
+
+ u32 PGCON;
+ u32 PGDAT;
+ u32 PGUP;
+
+ u32 OPENCR;
+
+ u32 MISCCR;
+ u32 EXTINT;
+#endif
+#ifdef CONFIG_S3C2410
+ u32 GPACON;
+ u32 GPADAT;
+ u32 res1[2];
+ u32 GPBCON;
+ u32 GPBDAT;
+ u32 GPBUP;
+ u32 res2;
+ u32 GPCCON;
+ u32 GPCDAT;
+ u32 GPCUP;
+ u32 res3;
+ u32 GPDCON;
+ u32 GPDDAT;
+ u32 GPDUP;
+ u32 res4;
+ u32 GPECON;
+ u32 GPEDAT;
+ u32 GPEUP;
+ u32 res5;
+ u32 GPFCON;
+ u32 GPFDAT;
+ u32 GPFUP;
+ u32 res6;
+ u32 GPGCON;
+ u32 GPGDAT;
+ u32 GPGUP;
+ u32 res7;
+ u32 GPHCON;
+ u32 GPHDAT;
+ u32 GPHUP;
+ u32 res8;
+
+ u32 MISCCR;
+ u32 DCLKCON;
+ u32 EXTINT0;
+ u32 EXTINT1;
+ u32 EXTINT2;
+ u32 EINTFLT0;
+ u32 EINTFLT1;
+ u32 EINTFLT2;
+ u32 EINTFLT3;
+ u32 EINTMASK;
+ u32 EINTPEND;
+ u32 GSTATUS0;
+ u32 GSTATUS1;
+ u32 GSTATUS2;
+ u32 GSTATUS3;
+ u32 GSTATUS4;
+#endif
+};
+
+
+/* RTC (see manual chapter 17) */
+struct s3c24x0_rtc {
+#ifdef __BIG_ENDIAN
+ u8 res1[67];
+ u8 RTCCON;
+ u8 res2[3];
+ u8 TICNT;
+ u8 res3[11];
+ u8 RTCALM;
+ u8 res4[3];
+ u8 ALMSEC;
+ u8 res5[3];
+ u8 ALMMIN;
+ u8 res6[3];
+ u8 ALMHOUR;
+ u8 res7[3];
+ u8 ALMDATE;
+ u8 res8[3];
+ u8 ALMMON;
+ u8 res9[3];
+ u8 ALMYEAR;
+ u8 res10[3];
+ u8 RTCRST;
+ u8 res11[3];
+ u8 BCDSEC;
+ u8 res12[3];
+ u8 BCDMIN;
+ u8 res13[3];
+ u8 BCDHOUR;
+ u8 res14[3];
+ u8 BCDDATE;
+ u8 res15[3];
+ u8 BCDDAY;
+ u8 res16[3];
+ u8 BCDMON;
+ u8 res17[3];
+ u8 BCDYEAR;
+#else /* little endian */
+ u8 res0[64];
+ u8 RTCCON;
+ u8 res1[3];
+ u8 TICNT;
+ u8 res2[11];
+ u8 RTCALM;
+ u8 res3[3];
+ u8 ALMSEC;
+ u8 res4[3];
+ u8 ALMMIN;
+ u8 res5[3];
+ u8 ALMHOUR;
+ u8 res6[3];
+ u8 ALMDATE;
+ u8 res7[3];
+ u8 ALMMON;
+ u8 res8[3];
+ u8 ALMYEAR;
+ u8 res9[3];
+ u8 RTCRST;
+ u8 res10[3];
+ u8 BCDSEC;
+ u8 res11[3];
+ u8 BCDMIN;
+ u8 res12[3];
+ u8 BCDHOUR;
+ u8 res13[3];
+ u8 BCDDATE;
+ u8 res14[3];
+ u8 BCDDAY;
+ u8 res15[3];
+ u8 BCDMON;
+ u8 res16[3];
+ u8 BCDYEAR;
+ u8 res17[3];
+#endif
+};
+
+
+/* ADC (see manual chapter 16) */
+struct s3c2400_adc {
+ u32 ADCCON;
+ u32 ADCDAT;
+};
+
+
+/* ADC (see manual chapter 16) */
+struct s3c2410_adc {
+ u32 ADCCON;
+ u32 ADCTSC;
+ u32 ADCDLY;
+ u32 ADCDAT0;
+ u32 ADCDAT1;
+};
+
+
+/* SPI (see manual chapter 22) */
+struct s3c24x0_spi_channel {
+ u8 SPCON;
+ u8 res1[3];
+ u8 SPSTA;
+ u8 res2[3];
+ u8 SPPIN;
+ u8 res3[3];
+ u8 SPPRE;
+ u8 res4[3];
+ u8 SPTDAT;
+ u8 res5[3];
+ u8 SPRDAT;
+ u8 res6[3];
+ u8 res7[16];
+};
+
+struct s3c24x0_spi {
+ struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS];
+};
+
+
+/* MMC INTERFACE (see S3C2400 manual chapter 19) */
+struct s3c2400_mmc {
+#ifdef __BIG_ENDIAN
+ u8 res1[3];
+ u8 MMCON;
+ u8 res2[3];
+ u8 MMCRR;
+ u8 res3[3];
+ u8 MMFCON;
+ u8 res4[3];
+ u8 MMSTA;
+ u16 res5;
+ u16 MMFSTA;
+ u8 res6[3];
+ u8 MMPRE;
+ u16 res7;
+ u16 MMLEN;
+ u8 res8[3];
+ u8 MMCR7;
+ u32 MMRSP[4];
+ u8 res9[3];
+ u8 MMCMD0;
+ u32 MMCMD1;
+ u16 res10;
+ u16 MMCR16;
+ u8 res11[3];
+ u8 MMDAT;
+#else
+ u8 MMCON;
+ u8 res1[3];
+ u8 MMCRR;
+ u8 res2[3];
+ u8 MMFCON;
+ u8 res3[3];
+ u8 MMSTA;
+ u8 res4[3];
+ u16 MMFSTA;
+ u16 res5;
+ u8 MMPRE;
+ u8 res6[3];
+ u16 MMLEN;
+ u16 res7;
+ u8 MMCR7;
+ u8 res8[3];
+ u32 MMRSP[4];
+ u8 MMCMD0;
+ u8 res9[3];
+ u32 MMCMD1;
+ u16 MMCR16;
+ u16 res10;
+ u8 MMDAT;
+ u8 res11[3];
+#endif
+};
+
+
+/* SD INTERFACE (see S3C2410 manual chapter 19) */
+struct s3c2410_sdi {
+ u32 SDICON;
+ u32 SDIPRE;
+ u32 SDICARG;
+ u32 SDICCON;
+ u32 SDICSTA;
+ u32 SDIRSP0;
+ u32 SDIRSP1;
+ u32 SDIRSP2;
+ u32 SDIRSP3;
+ u32 SDIDTIMER;
+ u32 SDIBSIZE;
+ u32 SDIDCON;
+ u32 SDIDCNT;
+ u32 SDIDSTA;
+ u32 SDIFSTA;
+#ifdef __BIG_ENDIAN
+ u8 res[3];
+ u8 SDIDAT;
+#else
+ u8 SDIDAT;
+ u8 res[3];
+#endif
+ u32 SDIIMSK;
+};
+
+#endif /*__S3C24X0_H__*/
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifdef CONFIG_S3C2400
+ #include <asm/arch/s3c2400.h>
+#elif defined CONFIG_S3C2410
+ #include <asm/arch/s3c2410.h>
+#else
+ #error Please define the s3c24x0 cpu type
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com.
+ * - only support for S3C6400
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME : s3c6400.h
+ *
+ * Based on S3C6400 User's manual Rev 0.0
+ ************************************************/
+
+#ifndef __S3C6400_H__
+#define __S3C6400_H__
+
+#define S3C64XX_UART_CHANNELS 3
+#define S3C64XX_SPI_CHANNELS 2
+
+#include <asm/hardware.h>
+
+#define ELFIN_CLOCK_POWER_BASE 0x7e00f000
+
+/* Clock & Power Controller for mDirac3*/
+#define APLL_LOCK_OFFSET 0x00
+#define MPLL_LOCK_OFFSET 0x04
+#define EPLL_LOCK_OFFSET 0x08
+#define APLL_CON_OFFSET 0x0C
+#define MPLL_CON_OFFSET 0x10
+#define EPLL_CON0_OFFSET 0x14
+#define EPLL_CON1_OFFSET 0x18
+#define CLK_SRC_OFFSET 0x1C
+#define CLK_DIV0_OFFSET 0x20
+#define CLK_DIV1_OFFSET 0x24
+#define CLK_DIV2_OFFSET 0x28
+#define CLK_OUT_OFFSET 0x2C
+#define HCLK_GATE_OFFSET 0x30
+#define PCLK_GATE_OFFSET 0x34
+#define SCLK_GATE_OFFSET 0x38
+#define AHB_CON0_OFFSET 0x100
+#define AHB_CON1_OFFSET 0x104
+#define AHB_CON2_OFFSET 0x108
+#define SELECT_DMA_OFFSET 0x110
+#define SW_RST_OFFSET 0x114
+#define SYS_ID_OFFSET 0x118
+#define MEM_SYS_CFG_OFFSET 0x120
+#define QOS_OVERRIDE0_OFFSET 0x124
+#define QOS_OVERRIDE1_OFFSET 0x128
+#define MEM_CFG_STAT_OFFSET 0x12C
+#define PWR_CFG_OFFSET 0x804
+#define EINT_MASK_OFFSET 0x808
+#define NOR_CFG_OFFSET 0x810
+#define STOP_CFG_OFFSET 0x814
+#define SLEEP_CFG_OFFSET 0x818
+#define OSC_FREQ_OFFSET 0x820
+#define OSC_STABLE_OFFSET 0x824
+#define PWR_STABLE_OFFSET 0x828
+#define FPC_STABLE_OFFSET 0x82C
+#define MTC_STABLE_OFFSET 0x830
+#define OTHERS_OFFSET 0x900
+#define RST_STAT_OFFSET 0x904
+#define WAKEUP_STAT_OFFSET 0x908
+#define BLK_PWR_STAT_OFFSET 0x90C
+#define INF_REG0_OFFSET 0xA00
+#define INF_REG1_OFFSET 0xA04
+#define INF_REG2_OFFSET 0xA08
+#define INF_REG3_OFFSET 0xA0C
+#define INF_REG4_OFFSET 0xA10
+#define INF_REG5_OFFSET 0xA14
+#define INF_REG6_OFFSET 0xA18
+#define INF_REG7_OFFSET 0xA1C
+
+#define OSC_CNT_VAL_OFFSET 0x824
+#define PWR_CNT_VAL_OFFSET 0x828
+#define FPC_CNT_VAL_OFFSET 0x82C
+#define MTC_CNT_VAL_OFFSET 0x830
+
+#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
+#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
+#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
+#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
+#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
+#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
+#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
+#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
+#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
+#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
+#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
+#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
+#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
+#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
+#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
+#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
+#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
+#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
+#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ SELECT_DMA_OFFSET)
+#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
+#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
+#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ MEM_SYS_CFG_OFFSET)
+#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ QOS_OVERRIDE0_OFFSET)
+#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ QOS_OVERRIDE1_OFFSET)
+#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ MEM_CFG_STAT_OFFSET)
+#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
+#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
+#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
+#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
+#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
+#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
+#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ OSC_CNT_VAL_OFFSET)
+#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ PWR_CNT_VAL_OFFSET)
+#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ FPC_CNT_VAL_OFFSET)
+#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ MTC_CNT_VAL_OFFSET)
+#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
+#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
+#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ WAKEUP_STAT_OFFSET)
+#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ BLK_PWR_STAT_OFFSET)
+#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
+#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
+#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
+#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
+#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
+#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
+#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
+#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
+
+#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
+#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
+#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
+#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
+#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
+#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
+#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
+#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
+#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
+#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
+#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
+#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
+#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
+#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
+#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
+#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
+#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
+#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
+#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET)
+#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
+#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
+#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET)
+#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET)
+#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET)
+#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET)
+#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
+#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
+#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
+#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
+#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
+#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
+#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET)
+#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET)
+#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET)
+#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET)
+#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
+#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
+#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
+#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET)
+#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
+#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
+#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
+#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
+#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
+#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
+#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
+#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
+
+
+/*
+ * GPIO
+ */
+#define ELFIN_GPIO_BASE 0x7f008000
+
+#define GPACON_OFFSET 0x00
+#define GPADAT_OFFSET 0x04
+#define GPAPUD_OFFSET 0x08
+#define GPACONSLP_OFFSET 0x0C
+#define GPAPUDSLP_OFFSET 0x10
+#define GPBCON_OFFSET 0x20
+#define GPBDAT_OFFSET 0x24
+#define GPBPUD_OFFSET 0x28
+#define GPBCONSLP_OFFSET 0x2C
+#define GPBPUDSLP_OFFSET 0x30
+#define GPCCON_OFFSET 0x40
+#define GPCDAT_OFFSET 0x44
+#define GPCPUD_OFFSET 0x48
+#define GPCCONSLP_OFFSET 0x4C
+#define GPCPUDSLP_OFFSET 0x50
+#define GPDCON_OFFSET 0x60
+#define GPDDAT_OFFSET 0x64
+#define GPDPUD_OFFSET 0x68
+#define GPDCONSLP_OFFSET 0x6C
+#define GPDPUDSLP_OFFSET 0x70
+#define GPECON_OFFSET 0x80
+#define GPEDAT_OFFSET 0x84
+#define GPEPUD_OFFSET 0x88
+#define GPECONSLP_OFFSET 0x8C
+#define GPEPUDSLP_OFFSET 0x90
+#define GPFCON_OFFSET 0xA0
+#define GPFDAT_OFFSET 0xA4
+#define GPFPUD_OFFSET 0xA8
+#define GPFCONSLP_OFFSET 0xAC
+#define GPFPUDSLP_OFFSET 0xB0
+#define GPGCON_OFFSET 0xC0
+#define GPGDAT_OFFSET 0xC4
+#define GPGPUD_OFFSET 0xC8
+#define GPGCONSLP_OFFSET 0xCC
+#define GPGPUDSLP_OFFSET 0xD0
+#define GPHCON0_OFFSET 0xE0
+#define GPHCON1_OFFSET 0xE4
+#define GPHDAT_OFFSET 0xE8
+#define GPHPUD_OFFSET 0xEC
+#define GPHCONSLP_OFFSET 0xF0
+#define GPHPUDSLP_OFFSET 0xF4
+#define GPICON_OFFSET 0x100
+#define GPIDAT_OFFSET 0x104
+#define GPIPUD_OFFSET 0x108
+#define GPICONSLP_OFFSET 0x10C
+#define GPIPUDSLP_OFFSET 0x110
+#define GPJCON_OFFSET 0x120
+#define GPJDAT_OFFSET 0x124
+#define GPJPUD_OFFSET 0x128
+#define GPJCONSLP_OFFSET 0x12C
+#define GPJPUDSLP_OFFSET 0x130
+#define MEM0DRVCON_OFFSET 0x1D0
+#define MEM1DRVCON_OFFSET 0x1D4
+#define GPKCON0_OFFSET 0x800
+#define GPKCON1_OFFSET 0x804
+#define GPKDAT_OFFSET 0x808
+#define GPKPUD_OFFSET 0x80C
+#define GPLCON0_OFFSET 0x810
+#define GPLCON1_OFFSET 0x814
+#define GPLDAT_OFFSET 0x818
+#define GPLPUD_OFFSET 0x81C
+#define GPMCON_OFFSET 0x820
+#define GPMDAT_OFFSET 0x824
+#define GPMPUD_OFFSET 0x828
+#define GPNCON_OFFSET 0x830
+#define GPNDAT_OFFSET 0x834
+#define GPNPUD_OFFSET 0x838
+#define GPOCON_OFFSET 0x140
+#define GPODAT_OFFSET 0x144
+#define GPOPUD_OFFSET 0x148
+#define GPOCONSLP_OFFSET 0x14C
+#define GPOPUDSLP_OFFSET 0x150
+#define GPPCON_OFFSET 0x160
+#define GPPDAT_OFFSET 0x164
+#define GPPPUD_OFFSET 0x168
+#define GPPCONSLP_OFFSET 0x16C
+#define GPPPUDSLP_OFFSET 0x170
+#define GPQCON_OFFSET 0x180
+#define GPQDAT_OFFSET 0x184
+#define GPQPUD_OFFSET 0x188
+#define GPQCONSLP_OFFSET 0x18C
+#define GPQPUDSLP_OFFSET 0x190
+
+#define EINTPEND_OFFSET 0x924
+
+#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET)
+#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET)
+#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET)
+#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
+#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
+#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET)
+#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET)
+#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET)
+#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
+#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
+#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET)
+#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET)
+#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET)
+#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
+#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
+#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET)
+#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET)
+#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET)
+#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
+#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
+#define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET)
+#define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET)
+#define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET)
+#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
+#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
+#define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET)
+#define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET)
+#define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET)
+#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
+#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
+#define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET)
+#define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET)
+#define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET)
+#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
+#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
+#define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET)
+#define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET)
+#define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET)
+#define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET)
+#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
+#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
+#define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET)
+#define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET)
+#define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET)
+#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
+#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
+#define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET)
+#define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET)
+#define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET)
+#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
+#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
+#define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
+#define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET)
+#define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET)
+#define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET)
+#define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET)
+#define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET)
+#define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET)
+#define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET)
+#define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET)
+#define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET)
+#define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET)
+#define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET)
+#define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET)
+#define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET)
+#define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET)
+#define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET)
+#define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET)
+#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
+#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
+#define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET)
+#define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET)
+#define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET)
+#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
+#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
+#define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET)
+#define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET)
+#define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET)
+#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
+#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
+
+/*
+ * Bus Matrix
+ */
+#define ELFIN_MEM_SYS_CFG 0x7e00f120
+
+#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12)
+
+#define S3C64XX_MEM_SYS_CFG_NAND 0x0008
+#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT
+
+#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET)
+#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET)
+#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET)
+#define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
+#define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
+#define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET)
+#define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET)
+#define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET)
+#define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
+#define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
+#define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET)
+#define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET)
+#define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET)
+#define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
+#define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
+#define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET)
+#define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET)
+#define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET)
+#define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
+#define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
+#define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET)
+#define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET)
+#define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET)
+#define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
+#define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
+#define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET)
+#define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET)
+#define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET)
+#define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
+#define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
+#define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET)
+#define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET)
+#define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET)
+#define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
+#define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
+#define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET)
+#define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET)
+#define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET)
+#define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET)
+#define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
+#define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
+#define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET)
+#define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET)
+#define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET)
+#define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
+#define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
+#define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET)
+#define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET)
+#define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET)
+#define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
+#define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
+#define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET)
+#define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET)
+#define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET)
+#define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET)
+#define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET)
+#define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET)
+#define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET)
+#define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET)
+#define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET)
+#define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET)
+#define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET)
+#define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET)
+#define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET)
+#define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET)
+#define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET)
+#define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET)
+#define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET)
+#define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
+#define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
+#define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET)
+#define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET)
+#define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET)
+#define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
+#define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
+#define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET)
+#define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET)
+#define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET)
+#define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
+#define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
+
+/*
+ * Memory controller
+ */
+#define ELFIN_SROM_BASE 0x70000000
+
+#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0)
+#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4)
+#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8)
+#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC)
+#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10)
+#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14)
+#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18)
+
+/*
+ * SDRAM Controller
+ */
+#define ELFIN_DMC0_BASE 0x7e000000
+#define ELFIN_DMC1_BASE 0x7e001000
+
+#define INDEX_DMC_MEMC_STATUS 0x00
+#define INDEX_DMC_MEMC_CMD 0x04
+#define INDEX_DMC_DIRECT_CMD 0x08
+#define INDEX_DMC_MEMORY_CFG 0x0C
+#define INDEX_DMC_REFRESH_PRD 0x10
+#define INDEX_DMC_CAS_LATENCY 0x14
+#define INDEX_DMC_T_DQSS 0x18
+#define INDEX_DMC_T_MRD 0x1C
+#define INDEX_DMC_T_RAS 0x20
+#define INDEX_DMC_T_RC 0x24
+#define INDEX_DMC_T_RCD 0x28
+#define INDEX_DMC_T_RFC 0x2C
+#define INDEX_DMC_T_RP 0x30
+#define INDEX_DMC_T_RRD 0x34
+#define INDEX_DMC_T_WR 0x38
+#define INDEX_DMC_T_WTR 0x3C
+#define INDEX_DMC_T_XP 0x40
+#define INDEX_DMC_T_XSR 0x44
+#define INDEX_DMC_T_ESR 0x48
+#define INDEX_DMC_MEMORY_CFG2 0x4C
+#define INDEX_DMC_CHIP_0_CFG 0x200
+#define INDEX_DMC_CHIP_1_CFG 0x204
+#define INDEX_DMC_CHIP_2_CFG 0x208
+#define INDEX_DMC_CHIP_3_CFG 0x20C
+#define INDEX_DMC_USER_STATUS 0x300
+#define INDEX_DMC_USER_CONFIG 0x304
+
+/*
+ * Memory Chip direct command
+ */
+#define DMC_NOP0 0x0c0000
+#define DMC_NOP1 0x1c0000
+#define DMC_PA0 0x000000 /* Precharge all */
+#define DMC_PA1 0x100000
+#define DMC_AR0 0x040000 /* Autorefresh */
+#define DMC_AR1 0x140000
+#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */
+#define DMC_SDR_MR1 0x180032
+#define DMC_DDR_MR0 0x080162
+#define DMC_DDR_MR1 0x180162
+#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */
+#define DMC_mDDR_MR1 0x180032
+#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */
+#define DMC_mSDR_EMR1 0x1a0000
+#define DMC_DDR_EMR0 0x090000
+#define DMC_DDR_EMR1 0x190000
+#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */
+#define DMC_mDDR_EMR1 0x1a0000
+
+/*
+ * Definitions for memory configuration
+ * Set memory configuration
+ * active_chips = 1'b0 (1 chip)
+ * qos_master_chip = 3'b000(ARID[3:0])
+ * memory burst = 3'b010(burst 4)
+ * stop_mem_clock = 1'b0(disable dynamical stop)
+ * auto_power_down = 1'b0(disable auto power-down mode)
+ * power_down_prd = 6'b00_0000(0 cycle for auto power-down)
+ * ap_bit = 1'b0 (bit position of auto-precharge is 10)
+ * row_bits = 3'b010(# row address 13)
+ * column_bits = 3'b010(# column address 10 )
+ *
+ * Set user configuration
+ * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR
+ *
+ * Set chip select for chip [n]
+ * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff
+ * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24]
+ */
+
+/*
+ * Nand flash controller
+ */
+#define ELFIN_NAND_BASE 0x70200000
+
+#define NFCONF_OFFSET 0x00
+#define NFCONT_OFFSET 0x04
+#define NFCMMD_OFFSET 0x08
+#define NFADDR_OFFSET 0x0c
+#define NFDATA_OFFSET 0x10
+#define NFMECCDATA0_OFFSET 0x14
+#define NFMECCDATA1_OFFSET 0x18
+#define NFSECCDATA0_OFFSET 0x1c
+#define NFSBLK_OFFSET 0x20
+#define NFEBLK_OFFSET 0x24
+#define NFSTAT_OFFSET 0x28
+#define NFESTAT0_OFFSET 0x2c
+#define NFESTAT1_OFFSET 0x30
+#define NFMECC0_OFFSET 0x34
+#define NFMECC1_OFFSET 0x38
+#define NFSECC_OFFSET 0x3c
+#define NFMLCBITPT_OFFSET 0x40
+
+#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET)
+#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET)
+#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET)
+#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET)
+#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET)
+#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
+#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
+#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
+#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET)
+#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET)
+#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET)
+#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET)
+#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET)
+#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET)
+#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET)
+#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET)
+#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
+
+#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET)
+#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET)
+#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET)
+#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET)
+#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET)
+#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET)
+#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
+#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
+#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
+#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET)
+#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET)
+#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET)
+#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET)
+#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET)
+#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET)
+#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET)
+#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET)
+#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
+
+#define NFCONF_ECC_4BIT (1<<24)
+
+#define NFCONT_ECC_ENC (1<<18)
+#define NFCONT_WP (1<<16)
+#define NFCONT_MECCLOCK (1<<7)
+#define NFCONT_SECCLOCK (1<<6)
+#define NFCONT_INITMECC (1<<5)
+#define NFCONT_INITSECC (1<<4)
+#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC)
+#define NFCONT_CS_ALT (1<<2)
+#define NFCONT_CS (1<<1)
+#define NFCONT_ENABLE (1<<0)
+
+#define NFSTAT_ECCENCDONE (1<<7)
+#define NFSTAT_ECCDECDONE (1<<6)
+#define NFSTAT_RnB (1<<0)
+
+#define NFESTAT0_ECCBUSY (1<<31)
+
+/*
+ * Interrupt
+ */
+#define ELFIN_VIC0_BASE_ADDR 0x71200000
+#define ELFIN_VIC1_BASE_ADDR 0x71300000
+#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */
+#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */
+#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */
+#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */
+#define oVECTADDR 0xF00 /* VIC ADDRESS */
+
+/*
+ * Watchdog timer
+ */
+#define ELFIN_WATCHDOG_BASE 0x7E004000
+
+#define WTCON_REG __REG(0x7E004004)
+#define WTDAT_REG __REG(0x7E004008)
+#define WTCNT_REG __REG(0x7E00400C)
+
+
+/*
+ * UART
+ */
+#define ELFIN_UART_BASE 0x7F005000
+
+#define ELFIN_UART0_OFFSET 0x0000
+#define ELFIN_UART1_OFFSET 0x0400
+#define ELFIN_UART2_OFFSET 0x0800
+
+#define ULCON_OFFSET 0x00
+#define UCON_OFFSET 0x04
+#define UFCON_OFFSET 0x08
+#define UMCON_OFFSET 0x0C
+#define UTRSTAT_OFFSET 0x10
+#define UERSTAT_OFFSET 0x14
+#define UFSTAT_OFFSET 0x18
+#define UMSTAT_OFFSET 0x1C
+#define UTXH_OFFSET 0x20
+#define URXH_OFFSET 0x24
+#define UBRDIV_OFFSET 0x28
+#define UDIVSLOT_OFFSET 0x2C
+#define UINTP_OFFSET 0x30
+#define UINTSP_OFFSET 0x34
+#define UINTM_OFFSET 0x38
+
+#define ULCON0_REG __REG(0x7F005000)
+#define UCON0_REG __REG(0x7F005004)
+#define UFCON0_REG __REG(0x7F005008)
+#define UMCON0_REG __REG(0x7F00500C)
+#define UTRSTAT0_REG __REG(0x7F005010)
+#define UERSTAT0_REG __REG(0x7F005014)
+#define UFSTAT0_REG __REG(0x7F005018)
+#define UMSTAT0_REG __REG(0x7F00501c)
+#define UTXH0_REG __REG(0x7F005020)
+#define URXH0_REG __REG(0x7F005024)
+#define UBRDIV0_REG __REG(0x7F005028)
+#define UDIVSLOT0_REG __REG(0x7F00502c)
+#define UINTP0_REG __REG(0x7F005030)
+#define UINTSP0_REG __REG(0x7F005034)
+#define UINTM0_REG __REG(0x7F005038)
+
+#define ULCON1_REG __REG(0x7F005400)
+#define UCON1_REG __REG(0x7F005404)
+#define UFCON1_REG __REG(0x7F005408)
+#define UMCON1_REG __REG(0x7F00540C)
+#define UTRSTAT1_REG __REG(0x7F005410)
+#define UERSTAT1_REG __REG(0x7F005414)
+#define UFSTAT1_REG __REG(0x7F005418)
+#define UMSTAT1_REG __REG(0x7F00541c)
+#define UTXH1_REG __REG(0x7F005420)
+#define URXH1_REG __REG(0x7F005424)
+#define UBRDIV1_REG __REG(0x7F005428)
+#define UDIVSLOT1_REG __REG(0x7F00542c)
+#define UINTP1_REG __REG(0x7F005430)
+#define UINTSP1_REG __REG(0x7F005434)
+#define UINTM1_REG __REG(0x7F005438)
+
+#define UTRSTAT_TX_EMPTY (1 << 2)
+#define UTRSTAT_RX_READY (1 << 0)
+#define UART_ERR_MASK 0xF
+
+/*
+ * PWM timer
+ */
+#define ELFIN_TIMER_BASE 0x7F006000
+
+#define TCFG0_REG __REG(0x7F006000)
+#define TCFG1_REG __REG(0x7F006004)
+#define TCON_REG __REG(0x7F006008)
+#define TCNTB0_REG __REG(0x7F00600c)
+#define TCMPB0_REG __REG(0x7F006010)
+#define TCNTO0_REG __REG(0x7F006014)
+#define TCNTB1_REG __REG(0x7F006018)
+#define TCMPB1_REG __REG(0x7F00601c)
+#define TCNTO1_REG __REG(0x7F006020)
+#define TCNTB2_REG __REG(0x7F006024)
+#define TCMPB2_REG __REG(0x7F006028)
+#define TCNTO2_REG __REG(0x7F00602c)
+#define TCNTB3_REG __REG(0x7F006030)
+#define TCMPB3_REG __REG(0x7F006034)
+#define TCNTO3_REG __REG(0x7F006038)
+#define TCNTB4_REG __REG(0x7F00603c)
+#define TCNTO4_REG __REG(0x7F006040)
+
+/* Fields */
+#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */
+#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */
+#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */
+#define fTCFG1_MUX4 Fld(4, 16)
+/* bits */
+#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE)
+#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1)
+#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0)
+#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */
+#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */
+#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */
+#define COUNT_4_ON (TCON_4_ONOFF * 1)
+#define COUNT_4_OFF (TCON_4_ONOFF * 0)
+#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */
+#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1)
+#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO)
+#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */
+#define TIMER3_IVT_ON (TCON_3_INVERT * 1)
+#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT))
+#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */
+#define TIMER3_MANUP (TCON_3_MAN*1)
+#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN))
+#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */
+#define TIMER3_ON (TCON_3_ONOFF * 1)
+#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF))
+
+#if defined(CONFIG_CLK_400_100_50)
+#define STARTUP_AMDIV 400
+#define STARTUP_MDIV 400
+#define STARTUP_PDIV 6
+#define STARTUP_SDIV 1
+#elif defined(CONFIG_CLK_400_133_66)
+#define STARTUP_AMDIV 400
+#define STARTUP_MDIV 533
+#define STARTUP_PDIV 6
+#define STARTUP_SDIV 1
+#elif defined(CONFIG_CLK_533_133_66)
+#define STARTUP_AMDIV 533
+#define STARTUP_MDIV 533
+#define STARTUP_PDIV 6
+#define STARTUP_SDIV 1
+#elif defined(CONFIG_CLK_667_133_66)
+#define STARTUP_AMDIV 667
+#define STARTUP_MDIV 533
+#define STARTUP_PDIV 6
+#define STARTUP_SDIV 1
+#endif
+
+#define STARTUP_PCLKDIV 3
+#define STARTUP_HCLKX2DIV 1
+#define STARTUP_HCLKDIV 1
+#define STARTUP_MPLLDIV 1
+#define STARTUP_APLLDIV 0
+
+#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \
+ (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV)
+#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
+ (STARTUP_PDIV << 8) | STARTUP_SDIV)
+#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
+ STARTUP_PDIV) * STARTUP_MDIV)
+
+#if defined(CONFIG_SYNC_MODE)
+#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
+ (STARTUP_PDIV << 8) | STARTUP_SDIV)
+#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
+ STARTUP_PDIV) * STARTUP_MDIV)
+#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
+ (STARTUP_HCLKDIV + 1))
+#else
+#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \
+ (STARTUP_PDIV << 8) | STARTUP_SDIV)
+#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
+ STARTUP_PDIV) * STARTUP_AMDIV)
+#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
+ (STARTUP_HCLKDIV + 1))
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */
+#define DMC1_MEM_CFG2 0xB45
+#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
+#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
+
+/* Memory Parameters */
+/* DDR Parameters */
+#define DDR_tREFRESH 7800 /* ns */
+#define DDR_tRAS 45 /* ns (min: 45ns)*/
+#define DDR_tRC 68 /* ns (min: 67.5ns)*/
+#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
+#define DDR_tRFC 80 /* ns (min: 80ns)*/
+#define DDR_tRP 23 /* ns (min: 22.5ns)*/
+#define DDR_tRRD 15 /* ns (min: 15ns)*/
+#define DDR_tWR 15 /* ns (min: 15ns)*/
+#define DDR_tXSR 120 /* ns (min: 120ns)*/
+#define DDR_CASL 3 /* CAS Latency 3 */
+
+/*
+ * mDDR memory configuration
+ */
+
+#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000)
+
+#define DMC_DDR_BA_EMRS 2
+#define DMC_DDR_MEM_CASLAT 3
+/* 6 Set Cas Latency to 3 */
+#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1)
+/* Min 0.75 ~ 1.25 */
+#define DMC_DDR_t_DQSS 1
+/* Min 2 tck */
+#define DMC_DDR_t_MRD 2
+/* 7, Min 45ns */
+#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1)
+/* 10, Min 67.5ns */
+#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1)
+/* 4,5(TRM), Min 22.5ns */
+#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1)
+#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3)
+/* 11,18(TRM) Min 80ns */
+#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1)
+#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5)
+/* 4, 5(TRM) Min 22.5ns */
+#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1)
+#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3)
+/* 3, Min 15ns */
+#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1)
+/* Min 15ns */
+#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1)
+#define DMC_DDR_t_WTR 2
+/* 1tck + tIS(1.5ns) */
+#define DMC_DDR_t_XP 2
+/* 17, Min 120ns */
+#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1)
+#define DMC_DDR_t_ESR DMC_DDR_t_XSR
+/* TRM 2656 */
+#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH))
+/* 2b01 : mDDR */
+#define DMC_DDR_USER_CONFIG 1
+
+#ifndef __ASSEMBLY__
+enum s3c64xx_uarts_nr {
+ S3C64XX_UART0,
+ S3C64XX_UART1,
+ S3C64XX_UART2,
+};
+
+#include "s3c64x0.h"
+
+static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr)
+{
+ return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400));
+}
+#endif
+
+#endif /*__S3C6400_H__*/
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * David MÃŒller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME : S3C64XX.h
+ * Version : 31.3.2003
+ *
+ * common stuff for SAMSUNG S3C64XX SoC
+ ************************************************/
+
+#ifndef __S3C64XX_H__
+#define __S3C64XX_H__
+
+#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400)
+#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration!
+#endif
+
+#include <asm/types.h>
+
+/* UART (see manual chapter 11) */
+typedef struct {
+ volatile u32 ULCON;
+ volatile u32 UCON;
+ volatile u32 UFCON;
+ volatile u32 UMCON;
+ volatile u32 UTRSTAT;
+ volatile u32 UERSTAT;
+ volatile u32 UFSTAT;
+ volatile u32 UMSTAT;
+#ifdef __BIG_ENDIAN
+ volatile u8 res1[3];
+ volatile u8 UTXH;
+ volatile u8 res2[3];
+ volatile u8 URXH;
+#else /* Little Endian */
+ volatile u8 UTXH;
+ volatile u8 res1[3];
+ volatile u8 URXH;
+ volatile u8 res2[3];
+#endif
+ volatile u32 UBRDIV;
+#ifdef __BIG_ENDIAN
+ volatile u8 res3[2];
+ volatile u16 UDIVSLOT;
+#else
+ volatile u16 UDIVSLOT;
+ volatile u8 res3[2];
+#endif
+} s3c64xx_uart;
+
+/* PWM TIMER (see manual chapter 10) */
+typedef struct {
+ volatile u32 TCNTB;
+ volatile u32 TCMPB;
+ volatile u32 TCNTO;
+} s3c64xx_timer;
+
+typedef struct {
+ volatile u32 TCFG0;
+ volatile u32 TCFG1;
+ volatile u32 TCON;
+ s3c64xx_timer ch[4];
+ volatile u32 TCNTB4;
+ volatile u32 TCNTO4;
+} s3c64xx_timers;
+
+#endif /*__S3C64XX_H__*/
/*
- * This was automagically generated from mach-types!
+ * This was automagically generated from arch/arm/tools/mach-types!
* Do NOT edit
- *
- * Last update: Fri Sep 4 22:16:22 2009
- *
*/
#ifndef __ASM_ARM_MACH_TYPE_H
#define MACH_TYPE_AML_M8050 1644
#define MACH_TYPE_MX35_3DS 1645
#define MACH_TYPE_MARS 1646
-#define MACH_TYPE_NTOSD_644XA 1647
+#define MACH_TYPE_NEUROS_OSD2 1647
#define MACH_TYPE_BADGER 1648
#define MACH_TYPE_TRIZEPS4WL 1649
#define MACH_TYPE_TRIZEPS5 1650
#define MACH_TYPE_ZORAN43XX 1660
#define MACH_TYPE_SONIX926 1661
#define MACH_TYPE_CELESTIALSEMI 1662
-#define MACH_TYPE_CC9M2443 1663
+#define MACH_TYPE_CC9M2443JS 1663
#define MACH_TYPE_TW5334 1664
#define MACH_TYPE_HTCARTEMIS 1665
#define MACH_TYPE_NAL_HLITE 1666
#define MACH_TYPE_WDG002 1785
#define MACH_TYPE_SG560ADSL 1786
#define MACH_TYPE_NEXTIO_N2800_ICA 1787
+#define MACH_TYPE_MACH_MARVELL_NEW1 1788
#define MACH_TYPE_MARVELL_NEWDB 1789
#define MACH_TYPE_VANDIHUD 1790
#define MACH_TYPE_MAGX_E8 1791
#define MACH_TYPE_RD88F5181L_GE 1812
#define MACH_TYPE_SIFMAIN 1813
#define MACH_TYPE_SAM9_L9261 1814
-#define MACH_TYPE_CC9M2443JS 1815
+#define MACH_TYPE_CC9M2443 1815
#define MACH_TYPE_XARIA300 1816
#define MACH_TYPE_IT9200 1817
#define MACH_TYPE_RD88F5181L_FXO 1818
#define MACH_TYPE_MULTIBUS_MASTER 2416
#define MACH_TYPE_MULTIBUS_PBK 2417
#define MACH_TYPE_TNETV107X 2418
+#define MACH_TYPE_SNAKE 2419
+#define MACH_TYPE_CWMX27 2420
+#define MACH_TYPE_SCH_M480 2421
+#define MACH_TYPE_PLATYPUS 2422
+#define MACH_TYPE_PSS2 2423
+#define MACH_TYPE_DAVINCI_APM150 2424
+#define MACH_TYPE_STR9100 2425
+#define MACH_TYPE_NET5BIG 2426
+#define MACH_TYPE_SEABED9263 2427
+#define MACH_TYPE_MX51_M2ID 2428
+#define MACH_TYPE_OCTVOCPLUS_EB 2429
+#define MACH_TYPE_KLK_FIREFOX 2430
+#define MACH_TYPE_KLK_WIRMA_MODULE 2431
+#define MACH_TYPE_KLK_WIRMA_MMI 2432
+#define MACH_TYPE_SUPERSONIC 2433
+#define MACH_TYPE_LIBERTY 2434
+#define MACH_TYPE_MH355 2435
+#define MACH_TYPE_PC7802 2436
+#define MACH_TYPE_GNET_SGC 2437
+#define MACH_TYPE_EINSTEIN15 2438
+#define MACH_TYPE_CMPD 2439
+#define MACH_TYPE_DAVINCI_HASE1 2440
+#define MACH_TYPE_LGEINCITEPHONE 2441
+#define MACH_TYPE_EA313X 2442
+#define MACH_TYPE_FWBD_39064 2443
+#define MACH_TYPE_FWBD_390128 2444
+#define MACH_TYPE_PELCO_MOE 2445
+#define MACH_TYPE_MINIMIX27 2446
+#define MACH_TYPE_OMAP3_THUNDER 2447
+#define MACH_TYPE_PASSIONC 2448
+#define MACH_TYPE_MX27AMATA 2449
+#define MACH_TYPE_BGAT1 2450
+#define MACH_TYPE_BUZZ 2451
+#define MACH_TYPE_MB9G20 2452
+#define MACH_TYPE_YUSHAN 2453
+#define MACH_TYPE_LIZARD 2454
+#define MACH_TYPE_OMAP3POLYCOM 2455
+#define MACH_TYPE_SMDKV210 2456
+#define MACH_TYPE_BRAVO 2457
+#define MACH_TYPE_SIOGENTOO1 2458
+#define MACH_TYPE_SIOGENTOO2 2459
+#define MACH_TYPE_SM3K 2460
+#define MACH_TYPE_ACER_TEMPO_F900 2461
+#define MACH_TYPE_SST61VC010_DEV 2462
+#define MACH_TYPE_GLITTERTIND 2463
+#define MACH_TYPE_OMAP_ZOOM3 2464
+#define MACH_TYPE_OMAP_3630SDP 2465
+#define MACH_TYPE_CYBOOK2440 2466
+#define MACH_TYPE_TORINO_S 2467
+#define MACH_TYPE_HAVANA 2468
+#define MACH_TYPE_BEAUMONT_11 2469
+#define MACH_TYPE_VANGUARD 2470
+#define MACH_TYPE_S5PC110_DRACO 2471
+#define MACH_TYPE_CARTESIO_TWO 2472
+#define MACH_TYPE_ASTER 2473
+#define MACH_TYPE_VOGUESV210 2474
+#define MACH_TYPE_ACM500X 2475
+#define MACH_TYPE_KM9260 2476
+#define MACH_TYPE_NIDEFLEXG1 2477
+#define MACH_TYPE_CTERA_PLUG_IO 2478
+#define MACH_TYPE_SMARTQ7 2479
+#define MACH_TYPE_AT91SAM9G10EK2 2480
+#define MACH_TYPE_ASUSP527 2481
+#define MACH_TYPE_AT91SAM9G20MPM2 2482
+#define MACH_TYPE_TOPASA900 2483
+#define MACH_TYPE_ELECTRUM_100 2484
+#define MACH_TYPE_MX51GRB 2485
+#define MACH_TYPE_XEA300 2486
+#define MACH_TYPE_HTCSTARTREK 2487
+#define MACH_TYPE_LIMA 2488
+#define MACH_TYPE_CSB740 2489
+#define MACH_TYPE_USB_S8815 2490
+#define MACH_TYPE_WATSON_EFM_PLUGIN 2491
+#define MACH_TYPE_MILKYWAY 2492
+#define MACH_TYPE_G4EVM 2493
+#define MACH_TYPE_PICOMOD6 2494
+#define MACH_TYPE_OMAPL138_HAWKBOARD 2495
+#define MACH_TYPE_IP6000 2496
+#define MACH_TYPE_IP6010 2497
+#define MACH_TYPE_UTM400 2498
+#define MACH_TYPE_OMAP3_ZYBEX 2499
+#define MACH_TYPE_WIRELESS_SPACE 2500
+#define MACH_TYPE_SX560 2501
+#define MACH_TYPE_TS41X 2502
+#define MACH_TYPE_ELPHEL10373 2503
+#define MACH_TYPE_RHOBOT 2504
+#define MACH_TYPE_MX51_REFRESH 2505
+#define MACH_TYPE_LS9260 2506
+#define MACH_TYPE_SHANK 2507
+#define MACH_TYPE_QSD8X50_ST1 2508
+#define MACH_TYPE_AT91SAM9M10EKES 2509
+#define MACH_TYPE_HIRAM 2510
+#define MACH_TYPE_PHY3250 2511
+#define MACH_TYPE_EA3250 2512
+#define MACH_TYPE_FDI3250 2513
+#define MACH_TYPE_WHITESTONE 2514
+#define MACH_TYPE_AT91SAM9263NIT 2515
+#define MACH_TYPE_CCMX51 2516
+#define MACH_TYPE_CCMX51JS 2517
+#define MACH_TYPE_CCWMX51 2518
+#define MACH_TYPE_CCWMX51JS 2519
+#define MACH_TYPE_MINI6410 2520
+#define MACH_TYPE_TINY6410 2521
+#define MACH_TYPE_NANO6410 2522
+#define MACH_TYPE_AT572D940HFNLDB 2523
+#define MACH_TYPE_HTCLEO 2524
+#define MACH_TYPE_AVP13 2525
+#define MACH_TYPE_XXSVIDEOD 2526
+#define MACH_TYPE_VPNEXT 2527
+#define MACH_TYPE_SWARCO_ITC3 2528
+#define MACH_TYPE_TX51 2529
+#define MACH_TYPE_DOLBY_CAT1021 2530
+#define MACH_TYPE_MX28EVK 2531
+#define MACH_TYPE_PHOENIX260 2532
+#define MACH_TYPE_UVACA_STORK 2533
+#define MACH_TYPE_SMARTQ5 2534
+#define MACH_TYPE_ALL3078 2535
+#define MACH_TYPE_CTERA_2BAY_DS 2536
+#define MACH_TYPE_SIOGENTOO3 2537
+#define MACH_TYPE_EPB5000 2538
+#define MACH_TYPE_HY9263 2539
+#define MACH_TYPE_ACER_TEMPO_M900 2540
+#define MACH_TYPE_ACER_TEMPO_DX900 2541
+#define MACH_TYPE_ACER_TEMPO_X960 2542
+#define MACH_TYPE_ACER_ETEN_V900 2543
+#define MACH_TYPE_ACER_ETEN_X900 2544
+#define MACH_TYPE_BONNELL 2545
+#define MACH_TYPE_OHT_MX27 2546
+#define MACH_TYPE_HTCQUARTZ 2547
+#define MACH_TYPE_DAVINCI_DM6467TEVM 2548
+#define MACH_TYPE_C3AX03 2549
+#define MACH_TYPE_MXT_TD60 2550
+#define MACH_TYPE_ESYX 2551
+#define MACH_TYPE_DOVE_DB 2552
+#define MACH_TYPE_BULLDOG 2553
+#define MACH_TYPE_DERELL_ME2000 2554
+#define MACH_TYPE_BCMRING_BASE 2555
+#define MACH_TYPE_BCMRING_EVM 2556
+#define MACH_TYPE_BCMRING_EVM_JAZZ 2557
+#define MACH_TYPE_BCMRING_SP 2558
+#define MACH_TYPE_BCMRING_SV 2559
+#define MACH_TYPE_BCMRING_SV_JAZZ 2560
+#define MACH_TYPE_BCMRING_TABLET 2561
+#define MACH_TYPE_BCMRING_VP 2562
+#define MACH_TYPE_BCMRING_EVM_SEIKOR 2563
+#define MACH_TYPE_BCMRING_SP_WQVGA 2564
+#define MACH_TYPE_BCMRING_CUSTOM 2565
+#define MACH_TYPE_ACER_S200 2566
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
# else
# define machine_arch_type MACH_TYPE_REA_2D
# endif
-# define machine_is_rea_2d() (machine_arch_type == MACH_TYPE_REA_2D)
+# define machine_is_rea_cpu2() (machine_arch_type == MACH_TYPE_REA_2D)
#else
-# define machine_is_rea_2d() (0)
+# define machine_is_rea_cpu2() (0)
#endif
#ifdef CONFIG_MACH_TI3E524
# define machine_is_mars() (0)
#endif
-#ifdef CONFIG_MACH_NTOSD_644XA
+#ifdef CONFIG_MACH_NEUROS_OSD2
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_NTOSD_644XA
+# define machine_arch_type MACH_TYPE_NEUROS_OSD2
# endif
-# define machine_is_ntosd_644xa() (machine_arch_type == MACH_TYPE_NTOSD_644XA)
+# define machine_is_neuros_osd2() (machine_arch_type == MACH_TYPE_NEUROS_OSD2)
#else
-# define machine_is_ntosd_644xa() (0)
+# define machine_is_neuros_osd2() (0)
#endif
#ifdef CONFIG_MACH_BADGER
# define machine_is_celestialsemi() (0)
#endif
-#ifdef CONFIG_MACH_CC9M2443
+#ifdef CONFIG_MACH_CC9M2443JS
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_CC9M2443
+# define machine_arch_type MACH_TYPE_CC9M2443JS
# endif
-# define machine_is_cc9m2443() (machine_arch_type == MACH_TYPE_CC9M2443)
+# define machine_is_cc9m2443js() (machine_arch_type == MACH_TYPE_CC9M2443JS)
#else
-# define machine_is_cc9m2443() (0)
+# define machine_is_cc9m2443js() (0)
#endif
#ifdef CONFIG_MACH_TW5334
# define machine_is_nextio_n2800_ica() (0)
#endif
+#ifdef CONFIG_MACH_MACH_MARVELL_NEW1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MACH_MARVELL_NEW1
+# endif
+# define machine_is_dove_db() (machine_arch_type == MACH_TYPE_MACH_MARVELL_NEW1)
+#else
+# define machine_is_dove_db() (0)
+#endif
+
#ifdef CONFIG_MACH_MARVELL_NEWDB
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_is_sam9_l9261() (0)
#endif
-#ifdef CONFIG_MACH_CC9M2443JS
+#ifdef CONFIG_MACH_CC9M2443
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_CC9M2443JS
+# define machine_arch_type MACH_TYPE_CC9M2443
# endif
-# define machine_is_cc9m2443js() (machine_arch_type == MACH_TYPE_CC9M2443JS)
+# define machine_is_cc9m2443() (machine_arch_type == MACH_TYPE_CC9M2443)
#else
-# define machine_is_cc9m2443js() (0)
+# define machine_is_cc9m2443() (0)
#endif
#ifdef CONFIG_MACH_XARIA300
# define machine_is_tnetv107x() (0)
#endif
+#ifdef CONFIG_MACH_SNAKE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SNAKE
+# endif
+# define machine_is_snake() (machine_arch_type == MACH_TYPE_SNAKE)
+#else
+# define machine_is_snake() (0)
+#endif
+
+#ifdef CONFIG_MACH_CWMX27
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CWMX27
+# endif
+# define machine_is_cwmx27() (machine_arch_type == MACH_TYPE_CWMX27)
+#else
+# define machine_is_cwmx27() (0)
+#endif
+
+#ifdef CONFIG_MACH_SCH_M480
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SCH_M480
+# endif
+# define machine_is_sch_m480() (machine_arch_type == MACH_TYPE_SCH_M480)
+#else
+# define machine_is_sch_m480() (0)
+#endif
+
+#ifdef CONFIG_MACH_PLATYPUS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PLATYPUS
+# endif
+# define machine_is_platypus() (machine_arch_type == MACH_TYPE_PLATYPUS)
+#else
+# define machine_is_platypus() (0)
+#endif
+
+#ifdef CONFIG_MACH_PSS2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PSS2
+# endif
+# define machine_is_pss2() (machine_arch_type == MACH_TYPE_PSS2)
+#else
+# define machine_is_pss2() (0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_APM150
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DAVINCI_APM150
+# endif
+# define machine_is_davinci_apm150() (machine_arch_type == MACH_TYPE_DAVINCI_APM150)
+#else
+# define machine_is_davinci_apm150() (0)
+#endif
+
+#ifdef CONFIG_MACH_STR9100
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_STR9100
+# endif
+# define machine_is_str9100() (machine_arch_type == MACH_TYPE_STR9100)
+#else
+# define machine_is_str9100() (0)
+#endif
+
+#ifdef CONFIG_MACH_NET5BIG
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NET5BIG
+# endif
+# define machine_is_net5big() (machine_arch_type == MACH_TYPE_NET5BIG)
+#else
+# define machine_is_net5big() (0)
+#endif
+
+#ifdef CONFIG_MACH_SEABED9263
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SEABED9263
+# endif
+# define machine_is_seabed9263() (machine_arch_type == MACH_TYPE_SEABED9263)
+#else
+# define machine_is_seabed9263() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_M2ID
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX51_M2ID
+# endif
+# define machine_is_mx51_m2id() (machine_arch_type == MACH_TYPE_MX51_M2ID)
+#else
+# define machine_is_mx51_m2id() (0)
+#endif
+
+#ifdef CONFIG_MACH_OCTVOCPLUS_EB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OCTVOCPLUS_EB
+# endif
+# define machine_is_octvocplus_eb() (machine_arch_type == MACH_TYPE_OCTVOCPLUS_EB)
+#else
+# define machine_is_octvocplus_eb() (0)
+#endif
+
+#ifdef CONFIG_MACH_KLK_FIREFOX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KLK_FIREFOX
+# endif
+# define machine_is_klk_firefox() (machine_arch_type == MACH_TYPE_KLK_FIREFOX)
+#else
+# define machine_is_klk_firefox() (0)
+#endif
+
+#ifdef CONFIG_MACH_KLK_WIRMA_MODULE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KLK_WIRMA_MODULE
+# endif
+# define machine_is_klk_wirma_module() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MODULE)
+#else
+# define machine_is_klk_wirma_module() (0)
+#endif
+
+#ifdef CONFIG_MACH_KLK_WIRMA_MMI
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KLK_WIRMA_MMI
+# endif
+# define machine_is_klk_wirma_mmi() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MMI)
+#else
+# define machine_is_klk_wirma_mmi() (0)
+#endif
+
+#ifdef CONFIG_MACH_SUPERSONIC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SUPERSONIC
+# endif
+# define machine_is_supersonic() (machine_arch_type == MACH_TYPE_SUPERSONIC)
+#else
+# define machine_is_supersonic() (0)
+#endif
+
+#ifdef CONFIG_MACH_LIBERTY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LIBERTY
+# endif
+# define machine_is_liberty() (machine_arch_type == MACH_TYPE_LIBERTY)
+#else
+# define machine_is_liberty() (0)
+#endif
+
+#ifdef CONFIG_MACH_MH355
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MH355
+# endif
+# define machine_is_mh355() (machine_arch_type == MACH_TYPE_MH355)
+#else
+# define machine_is_mh355() (0)
+#endif
+
+#ifdef CONFIG_MACH_PC7802
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PC7802
+# endif
+# define machine_is_pc7802() (machine_arch_type == MACH_TYPE_PC7802)
+#else
+# define machine_is_pc7802() (0)
+#endif
+
+#ifdef CONFIG_MACH_GNET_SGC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GNET_SGC
+# endif
+# define machine_is_gnet_sgc() (machine_arch_type == MACH_TYPE_GNET_SGC)
+#else
+# define machine_is_gnet_sgc() (0)
+#endif
+
+#ifdef CONFIG_MACH_EINSTEIN15
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EINSTEIN15
+# endif
+# define machine_is_einstein15() (machine_arch_type == MACH_TYPE_EINSTEIN15)
+#else
+# define machine_is_einstein15() (0)
+#endif
+
+#ifdef CONFIG_MACH_CMPD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CMPD
+# endif
+# define machine_is_cmpd() (machine_arch_type == MACH_TYPE_CMPD)
+#else
+# define machine_is_cmpd() (0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_HASE1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DAVINCI_HASE1
+# endif
+# define machine_is_davinci_hase1() (machine_arch_type == MACH_TYPE_DAVINCI_HASE1)
+#else
+# define machine_is_davinci_hase1() (0)
+#endif
+
+#ifdef CONFIG_MACH_LGEINCITEPHONE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LGEINCITEPHONE
+# endif
+# define machine_is_lgeincitephone() (machine_arch_type == MACH_TYPE_LGEINCITEPHONE)
+#else
+# define machine_is_lgeincitephone() (0)
+#endif
+
+#ifdef CONFIG_MACH_EA313X
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EA313X
+# endif
+# define machine_is_ea313x() (machine_arch_type == MACH_TYPE_EA313X)
+#else
+# define machine_is_ea313x() (0)
+#endif
+
+#ifdef CONFIG_MACH_FWBD_39064
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_FWBD_39064
+# endif
+# define machine_is_fwbd_39064() (machine_arch_type == MACH_TYPE_FWBD_39064)
+#else
+# define machine_is_fwbd_39064() (0)
+#endif
+
+#ifdef CONFIG_MACH_FWBD_390128
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_FWBD_390128
+# endif
+# define machine_is_fwbd_390128() (machine_arch_type == MACH_TYPE_FWBD_390128)
+#else
+# define machine_is_fwbd_390128() (0)
+#endif
+
+#ifdef CONFIG_MACH_PELCO_MOE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PELCO_MOE
+# endif
+# define machine_is_pelco_moe() (machine_arch_type == MACH_TYPE_PELCO_MOE)
+#else
+# define machine_is_pelco_moe() (0)
+#endif
+
+#ifdef CONFIG_MACH_MINIMIX27
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MINIMIX27
+# endif
+# define machine_is_minimix27() (machine_arch_type == MACH_TYPE_MINIMIX27)
+#else
+# define machine_is_minimix27() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_THUNDER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3_THUNDER
+# endif
+# define machine_is_omap3_thunder() (machine_arch_type == MACH_TYPE_OMAP3_THUNDER)
+#else
+# define machine_is_omap3_thunder() (0)
+#endif
+
+#ifdef CONFIG_MACH_PASSIONC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PASSIONC
+# endif
+# define machine_is_passionc() (machine_arch_type == MACH_TYPE_PASSIONC)
+#else
+# define machine_is_passionc() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX27AMATA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX27AMATA
+# endif
+# define machine_is_mx27amata() (machine_arch_type == MACH_TYPE_MX27AMATA)
+#else
+# define machine_is_mx27amata() (0)
+#endif
+
+#ifdef CONFIG_MACH_BGAT1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BGAT1
+# endif
+# define machine_is_bgat1() (machine_arch_type == MACH_TYPE_BGAT1)
+#else
+# define machine_is_bgat1() (0)
+#endif
+
+#ifdef CONFIG_MACH_BUZZ
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BUZZ
+# endif
+# define machine_is_buzz() (machine_arch_type == MACH_TYPE_BUZZ)
+#else
+# define machine_is_buzz() (0)
+#endif
+
+#ifdef CONFIG_MACH_MB9G20
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MB9G20
+# endif
+# define machine_is_mb9g20() (machine_arch_type == MACH_TYPE_MB9G20)
+#else
+# define machine_is_mb9g20() (0)
+#endif
+
+#ifdef CONFIG_MACH_YUSHAN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_YUSHAN
+# endif
+# define machine_is_yushan() (machine_arch_type == MACH_TYPE_YUSHAN)
+#else
+# define machine_is_yushan() (0)
+#endif
+
+#ifdef CONFIG_MACH_LIZARD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LIZARD
+# endif
+# define machine_is_lizard() (machine_arch_type == MACH_TYPE_LIZARD)
+#else
+# define machine_is_lizard() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3POLYCOM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3POLYCOM
+# endif
+# define machine_is_omap3polycom() (machine_arch_type == MACH_TYPE_OMAP3POLYCOM)
+#else
+# define machine_is_omap3polycom() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMDKV210
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMDKV210
+# endif
+# define machine_is_smdkv210() (machine_arch_type == MACH_TYPE_SMDKV210)
+#else
+# define machine_is_smdkv210() (0)
+#endif
+
+#ifdef CONFIG_MACH_BRAVO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BRAVO
+# endif
+# define machine_is_bravo() (machine_arch_type == MACH_TYPE_BRAVO)
+#else
+# define machine_is_bravo() (0)
+#endif
+
+#ifdef CONFIG_MACH_SIOGENTOO1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SIOGENTOO1
+# endif
+# define machine_is_siogentoo1() (machine_arch_type == MACH_TYPE_SIOGENTOO1)
+#else
+# define machine_is_siogentoo1() (0)
+#endif
+
+#ifdef CONFIG_MACH_SIOGENTOO2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SIOGENTOO2
+# endif
+# define machine_is_siogentoo2() (machine_arch_type == MACH_TYPE_SIOGENTOO2)
+#else
+# define machine_is_siogentoo2() (0)
+#endif
+
+#ifdef CONFIG_MACH_SM3K
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SM3K
+# endif
+# define machine_is_sm3k() (machine_arch_type == MACH_TYPE_SM3K)
+#else
+# define machine_is_sm3k() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_TEMPO_F900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_TEMPO_F900
+# endif
+# define machine_is_acer_tempo_f900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_F900)
+#else
+# define machine_is_acer_tempo_f900() (0)
+#endif
+
+#ifdef CONFIG_MACH_SST61VC010_DEV
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SST61VC010_DEV
+# endif
+# define machine_is_sst61vc010_dev() (machine_arch_type == MACH_TYPE_SST61VC010_DEV)
+#else
+# define machine_is_sst61vc010_dev() (0)
+#endif
+
+#ifdef CONFIG_MACH_GLITTERTIND
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GLITTERTIND
+# endif
+# define machine_is_glittertind() (machine_arch_type == MACH_TYPE_GLITTERTIND)
+#else
+# define machine_is_glittertind() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_ZOOM3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP_ZOOM3
+# endif
+# define machine_is_omap_zoom3() (machine_arch_type == MACH_TYPE_OMAP_ZOOM3)
+#else
+# define machine_is_omap_zoom3() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_3630SDP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP_3630SDP
+# endif
+# define machine_is_omap_3630sdp() (machine_arch_type == MACH_TYPE_OMAP_3630SDP)
+#else
+# define machine_is_omap_3630sdp() (0)
+#endif
+
+#ifdef CONFIG_MACH_CYBOOK2440
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CYBOOK2440
+# endif
+# define machine_is_cybook2440() (machine_arch_type == MACH_TYPE_CYBOOK2440)
+#else
+# define machine_is_cybook2440() (0)
+#endif
+
+#ifdef CONFIG_MACH_TORINO_S
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TORINO_S
+# endif
+# define machine_is_torino_s() (machine_arch_type == MACH_TYPE_TORINO_S)
+#else
+# define machine_is_torino_s() (0)
+#endif
+
+#ifdef CONFIG_MACH_HAVANA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HAVANA
+# endif
+# define machine_is_havana() (machine_arch_type == MACH_TYPE_HAVANA)
+#else
+# define machine_is_havana() (0)
+#endif
+
+#ifdef CONFIG_MACH_BEAUMONT_11
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BEAUMONT_11
+# endif
+# define machine_is_beaumont_11() (machine_arch_type == MACH_TYPE_BEAUMONT_11)
+#else
+# define machine_is_beaumont_11() (0)
+#endif
+
+#ifdef CONFIG_MACH_VANGUARD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VANGUARD
+# endif
+# define machine_is_vanguard() (machine_arch_type == MACH_TYPE_VANGUARD)
+#else
+# define machine_is_vanguard() (0)
+#endif
+
+#ifdef CONFIG_MACH_S5PC110_DRACO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_S5PC110_DRACO
+# endif
+# define machine_is_s5pc110_draco() (machine_arch_type == MACH_TYPE_S5PC110_DRACO)
+#else
+# define machine_is_s5pc110_draco() (0)
+#endif
+
+#ifdef CONFIG_MACH_CARTESIO_TWO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CARTESIO_TWO
+# endif
+# define machine_is_cartesio_two() (machine_arch_type == MACH_TYPE_CARTESIO_TWO)
+#else
+# define machine_is_cartesio_two() (0)
+#endif
+
+#ifdef CONFIG_MACH_ASTER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ASTER
+# endif
+# define machine_is_aster() (machine_arch_type == MACH_TYPE_ASTER)
+#else
+# define machine_is_aster() (0)
+#endif
+
+#ifdef CONFIG_MACH_VOGUESV210
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VOGUESV210
+# endif
+# define machine_is_voguesv210() (machine_arch_type == MACH_TYPE_VOGUESV210)
+#else
+# define machine_is_voguesv210() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACM500X
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACM500X
+# endif
+# define machine_is_acm500x() (machine_arch_type == MACH_TYPE_ACM500X)
+#else
+# define machine_is_acm500x() (0)
+#endif
+
+#ifdef CONFIG_MACH_KM9260
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KM9260
+# endif
+# define machine_is_km9260() (machine_arch_type == MACH_TYPE_KM9260)
+#else
+# define machine_is_km9260() (0)
+#endif
+
+#ifdef CONFIG_MACH_NIDEFLEXG1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NIDEFLEXG1
+# endif
+# define machine_is_nideflexg1() (machine_arch_type == MACH_TYPE_NIDEFLEXG1)
+#else
+# define machine_is_nideflexg1() (0)
+#endif
+
+#ifdef CONFIG_MACH_CTERA_PLUG_IO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CTERA_PLUG_IO
+# endif
+# define machine_is_ctera_plug_io() (machine_arch_type == MACH_TYPE_CTERA_PLUG_IO)
+#else
+# define machine_is_ctera_plug_io() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTQ7
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMARTQ7
+# endif
+# define machine_is_smartq7() (machine_arch_type == MACH_TYPE_SMARTQ7)
+#else
+# define machine_is_smartq7() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9G10EK2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9G10EK2
+# endif
+# define machine_is_at91sam9g10ek2() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK2)
+#else
+# define machine_is_at91sam9g10ek2() (0)
+#endif
+
+#ifdef CONFIG_MACH_ASUSP527
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ASUSP527
+# endif
+# define machine_is_asusp527() (machine_arch_type == MACH_TYPE_ASUSP527)
+#else
+# define machine_is_asusp527() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9G20MPM2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9G20MPM2
+# endif
+# define machine_is_at91sam9g20mpm2() (machine_arch_type == MACH_TYPE_AT91SAM9G20MPM2)
+#else
+# define machine_is_at91sam9g20mpm2() (0)
+#endif
+
+#ifdef CONFIG_MACH_TOPASA900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TOPASA900
+# endif
+# define machine_is_topasa900() (machine_arch_type == MACH_TYPE_TOPASA900)
+#else
+# define machine_is_topasa900() (0)
+#endif
+
+#ifdef CONFIG_MACH_ELECTRUM_100
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ELECTRUM_100
+# endif
+# define machine_is_electrum_100() (machine_arch_type == MACH_TYPE_ELECTRUM_100)
+#else
+# define machine_is_electrum_100() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX51GRB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX51GRB
+# endif
+# define machine_is_mx51grb() (machine_arch_type == MACH_TYPE_MX51GRB)
+#else
+# define machine_is_mx51grb() (0)
+#endif
+
+#ifdef CONFIG_MACH_XEA300
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_XEA300
+# endif
+# define machine_is_xea300() (machine_arch_type == MACH_TYPE_XEA300)
+#else
+# define machine_is_xea300() (0)
+#endif
+
+#ifdef CONFIG_MACH_HTCSTARTREK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HTCSTARTREK
+# endif
+# define machine_is_htcstartrek() (machine_arch_type == MACH_TYPE_HTCSTARTREK)
+#else
+# define machine_is_htcstartrek() (0)
+#endif
+
+#ifdef CONFIG_MACH_LIMA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LIMA
+# endif
+# define machine_is_lima() (machine_arch_type == MACH_TYPE_LIMA)
+#else
+# define machine_is_lima() (0)
+#endif
+
+#ifdef CONFIG_MACH_CSB740
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CSB740
+# endif
+# define machine_is_csb740() (machine_arch_type == MACH_TYPE_CSB740)
+#else
+# define machine_is_csb740() (0)
+#endif
+
+#ifdef CONFIG_MACH_USB_S8815
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_USB_S8815
+# endif
+# define machine_is_usb_s8815() (machine_arch_type == MACH_TYPE_USB_S8815)
+#else
+# define machine_is_usb_s8815() (0)
+#endif
+
+#ifdef CONFIG_MACH_WATSON_EFM_PLUGIN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WATSON_EFM_PLUGIN
+# endif
+# define machine_is_watson_efm_plugin() (machine_arch_type == MACH_TYPE_WATSON_EFM_PLUGIN)
+#else
+# define machine_is_watson_efm_plugin() (0)
+#endif
+
+#ifdef CONFIG_MACH_MILKYWAY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MILKYWAY
+# endif
+# define machine_is_milkyway() (machine_arch_type == MACH_TYPE_MILKYWAY)
+#else
+# define machine_is_milkyway() (0)
+#endif
+
+#ifdef CONFIG_MACH_G4EVM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_G4EVM
+# endif
+# define machine_is_g4evm() (machine_arch_type == MACH_TYPE_G4EVM)
+#else
+# define machine_is_g4evm() (0)
+#endif
+
+#ifdef CONFIG_MACH_PICOMOD6
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PICOMOD6
+# endif
+# define machine_is_picomod6() (machine_arch_type == MACH_TYPE_PICOMOD6)
+#else
+# define machine_is_picomod6() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAPL138_HAWKBOARD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAPL138_HAWKBOARD
+# endif
+# define machine_is_omapl138_hawkboard() (machine_arch_type == MACH_TYPE_OMAPL138_HAWKBOARD)
+#else
+# define machine_is_omapl138_hawkboard() (0)
+#endif
+
+#ifdef CONFIG_MACH_IP6000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IP6000
+# endif
+# define machine_is_ip6000() (machine_arch_type == MACH_TYPE_IP6000)
+#else
+# define machine_is_ip6000() (0)
+#endif
+
+#ifdef CONFIG_MACH_IP6010
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IP6010
+# endif
+# define machine_is_ip6010() (machine_arch_type == MACH_TYPE_IP6010)
+#else
+# define machine_is_ip6010() (0)
+#endif
+
+#ifdef CONFIG_MACH_UTM400
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_UTM400
+# endif
+# define machine_is_utm400() (machine_arch_type == MACH_TYPE_UTM400)
+#else
+# define machine_is_utm400() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_ZYBEX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3_ZYBEX
+# endif
+# define machine_is_omap3_zybex() (machine_arch_type == MACH_TYPE_OMAP3_ZYBEX)
+#else
+# define machine_is_omap3_zybex() (0)
+#endif
+
+#ifdef CONFIG_MACH_WIRELESS_SPACE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WIRELESS_SPACE
+# endif
+# define machine_is_wireless_space() (machine_arch_type == MACH_TYPE_WIRELESS_SPACE)
+#else
+# define machine_is_wireless_space() (0)
+#endif
+
+#ifdef CONFIG_MACH_SX560
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SX560
+# endif
+# define machine_is_sx560() (machine_arch_type == MACH_TYPE_SX560)
+#else
+# define machine_is_sx560() (0)
+#endif
+
+#ifdef CONFIG_MACH_TS41X
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TS41X
+# endif
+# define machine_is_ts41x() (machine_arch_type == MACH_TYPE_TS41X)
+#else
+# define machine_is_ts41x() (0)
+#endif
+
+#ifdef CONFIG_MACH_ELPHEL10373
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ELPHEL10373
+# endif
+# define machine_is_elphel10373() (machine_arch_type == MACH_TYPE_ELPHEL10373)
+#else
+# define machine_is_elphel10373() (0)
+#endif
+
+#ifdef CONFIG_MACH_RHOBOT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_RHOBOT
+# endif
+# define machine_is_rhobot() (machine_arch_type == MACH_TYPE_RHOBOT)
+#else
+# define machine_is_rhobot() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_REFRESH
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX51_REFRESH
+# endif
+# define machine_is_mx51_refresh() (machine_arch_type == MACH_TYPE_MX51_REFRESH)
+#else
+# define machine_is_mx51_refresh() (0)
+#endif
+
+#ifdef CONFIG_MACH_LS9260
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LS9260
+# endif
+# define machine_is_ls9260() (machine_arch_type == MACH_TYPE_LS9260)
+#else
+# define machine_is_ls9260() (0)
+#endif
+
+#ifdef CONFIG_MACH_SHANK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SHANK
+# endif
+# define machine_is_shank() (machine_arch_type == MACH_TYPE_SHANK)
+#else
+# define machine_is_shank() (0)
+#endif
+
+#ifdef CONFIG_MACH_QSD8X50_ST1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_QSD8X50_ST1
+# endif
+# define machine_is_qsd8x50_st1() (machine_arch_type == MACH_TYPE_QSD8X50_ST1)
+#else
+# define machine_is_qsd8x50_st1() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9M10EKES
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9M10EKES
+# endif
+# define machine_is_at91sam9m10ekes() (machine_arch_type == MACH_TYPE_AT91SAM9M10EKES)
+#else
+# define machine_is_at91sam9m10ekes() (0)
+#endif
+
+#ifdef CONFIG_MACH_HIRAM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HIRAM
+# endif
+# define machine_is_hiram() (machine_arch_type == MACH_TYPE_HIRAM)
+#else
+# define machine_is_hiram() (0)
+#endif
+
+#ifdef CONFIG_MACH_PHY3250
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PHY3250
+# endif
+# define machine_is_phy3250() (machine_arch_type == MACH_TYPE_PHY3250)
+#else
+# define machine_is_phy3250() (0)
+#endif
+
+#ifdef CONFIG_MACH_EA3250
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EA3250
+# endif
+# define machine_is_ea3250() (machine_arch_type == MACH_TYPE_EA3250)
+#else
+# define machine_is_ea3250() (0)
+#endif
+
+#ifdef CONFIG_MACH_FDI3250
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_FDI3250
+# endif
+# define machine_is_fdi3250() (machine_arch_type == MACH_TYPE_FDI3250)
+#else
+# define machine_is_fdi3250() (0)
+#endif
+
+#ifdef CONFIG_MACH_WHITESTONE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WHITESTONE
+# endif
+# define machine_is_whitestone() (machine_arch_type == MACH_TYPE_WHITESTONE)
+#else
+# define machine_is_whitestone() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9263NIT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9263NIT
+# endif
+# define machine_is_at91sam9263nit() (machine_arch_type == MACH_TYPE_AT91SAM9263NIT)
+#else
+# define machine_is_at91sam9263nit() (0)
+#endif
+
+#ifdef CONFIG_MACH_CCMX51
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CCMX51
+# endif
+# define machine_is_ccmx51() (machine_arch_type == MACH_TYPE_CCMX51)
+#else
+# define machine_is_ccmx51() (0)
+#endif
+
+#ifdef CONFIG_MACH_CCMX51JS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CCMX51JS
+# endif
+# define machine_is_ccmx51js() (machine_arch_type == MACH_TYPE_CCMX51JS)
+#else
+# define machine_is_ccmx51js() (0)
+#endif
+
+#ifdef CONFIG_MACH_CCWMX51
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CCWMX51
+# endif
+# define machine_is_ccwmx51() (machine_arch_type == MACH_TYPE_CCWMX51)
+#else
+# define machine_is_ccwmx51() (0)
+#endif
+
+#ifdef CONFIG_MACH_CCWMX51JS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CCWMX51JS
+# endif
+# define machine_is_ccwmx51js() (machine_arch_type == MACH_TYPE_CCWMX51JS)
+#else
+# define machine_is_ccwmx51js() (0)
+#endif
+
+#ifdef CONFIG_MACH_MINI6410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MINI6410
+# endif
+# define machine_is_mini6410() (machine_arch_type == MACH_TYPE_MINI6410)
+#else
+# define machine_is_mini6410() (0)
+#endif
+
+#ifdef CONFIG_MACH_TINY6410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TINY6410
+# endif
+# define machine_is_tiny6410() (machine_arch_type == MACH_TYPE_TINY6410)
+#else
+# define machine_is_tiny6410() (0)
+#endif
+
+#ifdef CONFIG_MACH_NANO6410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NANO6410
+# endif
+# define machine_is_nano6410() (machine_arch_type == MACH_TYPE_NANO6410)
+#else
+# define machine_is_nano6410() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT572D940HFNLDB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT572D940HFNLDB
+# endif
+# define machine_is_at572d940hfnldb() (machine_arch_type == MACH_TYPE_AT572D940HFNLDB)
+#else
+# define machine_is_at572d940hfnldb() (0)
+#endif
+
+#ifdef CONFIG_MACH_HTCLEO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HTCLEO
+# endif
+# define machine_is_htcleo() (machine_arch_type == MACH_TYPE_HTCLEO)
+#else
+# define machine_is_htcleo() (0)
+#endif
+
+#ifdef CONFIG_MACH_AVP13
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AVP13
+# endif
+# define machine_is_avp13() (machine_arch_type == MACH_TYPE_AVP13)
+#else
+# define machine_is_avp13() (0)
+#endif
+
+#ifdef CONFIG_MACH_XXSVIDEOD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_XXSVIDEOD
+# endif
+# define machine_is_xxsvideod() (machine_arch_type == MACH_TYPE_XXSVIDEOD)
+#else
+# define machine_is_xxsvideod() (0)
+#endif
+
+#ifdef CONFIG_MACH_VPNEXT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VPNEXT
+# endif
+# define machine_is_vpnext() (machine_arch_type == MACH_TYPE_VPNEXT)
+#else
+# define machine_is_vpnext() (0)
+#endif
+
+#ifdef CONFIG_MACH_SWARCO_ITC3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SWARCO_ITC3
+# endif
+# define machine_is_swarco_itc3() (machine_arch_type == MACH_TYPE_SWARCO_ITC3)
+#else
+# define machine_is_swarco_itc3() (0)
+#endif
+
+#ifdef CONFIG_MACH_TX51
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TX51
+# endif
+# define machine_is_tx51() (machine_arch_type == MACH_TYPE_TX51)
+#else
+# define machine_is_tx51() (0)
+#endif
+
+#ifdef CONFIG_MACH_DOLBY_CAT1021
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DOLBY_CAT1021
+# endif
+# define machine_is_dolby_cat1021() (machine_arch_type == MACH_TYPE_DOLBY_CAT1021)
+#else
+# define machine_is_dolby_cat1021() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX28EVK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX28EVK
+# endif
+# define machine_is_mx28evk() (machine_arch_type == MACH_TYPE_MX28EVK)
+#else
+# define machine_is_mx28evk() (0)
+#endif
+
+#ifdef CONFIG_MACH_PHOENIX260
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PHOENIX260
+# endif
+# define machine_is_phoenix260() (machine_arch_type == MACH_TYPE_PHOENIX260)
+#else
+# define machine_is_phoenix260() (0)
+#endif
+
+#ifdef CONFIG_MACH_UVACA_STORK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_UVACA_STORK
+# endif
+# define machine_is_uvaca_stork() (machine_arch_type == MACH_TYPE_UVACA_STORK)
+#else
+# define machine_is_uvaca_stork() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTQ5
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMARTQ5
+# endif
+# define machine_is_smartq5() (machine_arch_type == MACH_TYPE_SMARTQ5)
+#else
+# define machine_is_smartq5() (0)
+#endif
+
+#ifdef CONFIG_MACH_ALL3078
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ALL3078
+# endif
+# define machine_is_all3078() (machine_arch_type == MACH_TYPE_ALL3078)
+#else
+# define machine_is_all3078() (0)
+#endif
+
+#ifdef CONFIG_MACH_CTERA_2BAY_DS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CTERA_2BAY_DS
+# endif
+# define machine_is_ctera_2bay_ds() (machine_arch_type == MACH_TYPE_CTERA_2BAY_DS)
+#else
+# define machine_is_ctera_2bay_ds() (0)
+#endif
+
+#ifdef CONFIG_MACH_SIOGENTOO3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SIOGENTOO3
+# endif
+# define machine_is_siogentoo3() (machine_arch_type == MACH_TYPE_SIOGENTOO3)
+#else
+# define machine_is_siogentoo3() (0)
+#endif
+
+#ifdef CONFIG_MACH_EPB5000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EPB5000
+# endif
+# define machine_is_epb5000() (machine_arch_type == MACH_TYPE_EPB5000)
+#else
+# define machine_is_epb5000() (0)
+#endif
+
+#ifdef CONFIG_MACH_HY9263
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HY9263
+# endif
+# define machine_is_hy9263() (machine_arch_type == MACH_TYPE_HY9263)
+#else
+# define machine_is_hy9263() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_TEMPO_M900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_TEMPO_M900
+# endif
+# define machine_is_acer_tempo_m900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_M900)
+#else
+# define machine_is_acer_tempo_m900() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_TEMPO_DX900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_TEMPO_DX900
+# endif
+# define machine_is_acer_tempo_dx650() (machine_arch_type == MACH_TYPE_ACER_TEMPO_DX900)
+#else
+# define machine_is_acer_tempo_dx650() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_TEMPO_X960
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_TEMPO_X960
+# endif
+# define machine_is_acer_tempo_x960() (machine_arch_type == MACH_TYPE_ACER_TEMPO_X960)
+#else
+# define machine_is_acer_tempo_x960() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_ETEN_V900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_ETEN_V900
+# endif
+# define machine_is_acer_eten_v900() (machine_arch_type == MACH_TYPE_ACER_ETEN_V900)
+#else
+# define machine_is_acer_eten_v900() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_ETEN_X900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_ETEN_X900
+# endif
+# define machine_is_acer_eten_x900() (machine_arch_type == MACH_TYPE_ACER_ETEN_X900)
+#else
+# define machine_is_acer_eten_x900() (0)
+#endif
+
+#ifdef CONFIG_MACH_BONNELL
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BONNELL
+# endif
+# define machine_is_bonnell() (machine_arch_type == MACH_TYPE_BONNELL)
+#else
+# define machine_is_bonnell() (0)
+#endif
+
+#ifdef CONFIG_MACH_OHT_MX27
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OHT_MX27
+# endif
+# define machine_is_oht_mx27() (machine_arch_type == MACH_TYPE_OHT_MX27)
+#else
+# define machine_is_oht_mx27() (0)
+#endif
+
+#ifdef CONFIG_MACH_HTCQUARTZ
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HTCQUARTZ
+# endif
+# define machine_is_htcquartz() (machine_arch_type == MACH_TYPE_HTCQUARTZ)
+#else
+# define machine_is_htcquartz() (0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DM6467TEVM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DAVINCI_DM6467TEVM
+# endif
+# define machine_is_davinci_dm6467tevm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467TEVM)
+#else
+# define machine_is_davinci_dm6467tevm() (0)
+#endif
+
+#ifdef CONFIG_MACH_C3AX03
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_C3AX03
+# endif
+# define machine_is_c3ax03() (machine_arch_type == MACH_TYPE_C3AX03)
+#else
+# define machine_is_c3ax03() (0)
+#endif
+
+#ifdef CONFIG_MACH_MXT_TD60
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MXT_TD60
+# endif
+# define machine_is_mxt_td60() (machine_arch_type == MACH_TYPE_MXT_TD60)
+#else
+# define machine_is_mxt_td60() (0)
+#endif
+
+#ifdef CONFIG_MACH_ESYX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ESYX
+# endif
+# define machine_is_esyx() (machine_arch_type == MACH_TYPE_ESYX)
+#else
+# define machine_is_esyx() (0)
+#endif
+
+#ifdef CONFIG_MACH_DOVE_DB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DOVE_DB
+# endif
+# define machine_is_dove_db2() (machine_arch_type == MACH_TYPE_DOVE_DB)
+#else
+# define machine_is_dove_db2() (0)
+#endif
+
+#ifdef CONFIG_MACH_BULLDOG
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BULLDOG
+# endif
+# define machine_is_bulldog() (machine_arch_type == MACH_TYPE_BULLDOG)
+#else
+# define machine_is_bulldog() (0)
+#endif
+
+#ifdef CONFIG_MACH_DERELL_ME2000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DERELL_ME2000
+# endif
+# define machine_is_derell_me2000() (machine_arch_type == MACH_TYPE_DERELL_ME2000)
+#else
+# define machine_is_derell_me2000() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_BASE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_BASE
+# endif
+# define machine_is_bcmring_base() (machine_arch_type == MACH_TYPE_BCMRING_BASE)
+#else
+# define machine_is_bcmring_base() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_EVM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_EVM
+# endif
+# define machine_is_bcmring_evm() (machine_arch_type == MACH_TYPE_BCMRING_EVM)
+#else
+# define machine_is_bcmring_evm() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_EVM_JAZZ
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_EVM_JAZZ
+# endif
+# define machine_is_bcmring_evm_jazz() (machine_arch_type == MACH_TYPE_BCMRING_EVM_JAZZ)
+#else
+# define machine_is_bcmring_evm_jazz() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_SP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_SP
+# endif
+# define machine_is_bcmring_sp() (machine_arch_type == MACH_TYPE_BCMRING_SP)
+#else
+# define machine_is_bcmring_sp() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_SV
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_SV
+# endif
+# define machine_is_bcmring_sv() (machine_arch_type == MACH_TYPE_BCMRING_SV)
+#else
+# define machine_is_bcmring_sv() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_SV_JAZZ
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_SV_JAZZ
+# endif
+# define machine_is_bcmring_sv_jazz() (machine_arch_type == MACH_TYPE_BCMRING_SV_JAZZ)
+#else
+# define machine_is_bcmring_sv_jazz() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_TABLET
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_TABLET
+# endif
+# define machine_is_bcmring_tablet() (machine_arch_type == MACH_TYPE_BCMRING_TABLET)
+#else
+# define machine_is_bcmring_tablet() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_VP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_VP
+# endif
+# define machine_is_bcmring_vp() (machine_arch_type == MACH_TYPE_BCMRING_VP)
+#else
+# define machine_is_bcmring_vp() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_EVM_SEIKOR
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_EVM_SEIKOR
+# endif
+# define machine_is_bcmring_evm_seikor() (machine_arch_type == MACH_TYPE_BCMRING_EVM_SEIKOR)
+#else
+# define machine_is_bcmring_evm_seikor() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_SP_WQVGA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_SP_WQVGA
+# endif
+# define machine_is_bcmring_sp_wqvga() (machine_arch_type == MACH_TYPE_BCMRING_SP_WQVGA)
+#else
+# define machine_is_bcmring_sp_wqvga() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_CUSTOM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_CUSTOM
+# endif
+# define machine_is_bcmring_custom() (machine_arch_type == MACH_TYPE_BCMRING_CUSTOM)
+#else
+# define machine_is_bcmring_custom() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_S200
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_S200
+# endif
+# define machine_is_acer_s200() (machine_arch_type == MACH_TYPE_ACER_S200)
+#else
+# define machine_is_acer_s200() (0)
+#endif
+
/*
* These have not yet been registered
*/
#ifdef CONFIG_BLACKFIN
#include <asm/blackfin.h>
#endif
+#ifdef CONFIG_SOC_DA8XX
+#include <asm/arch/hardware.h>
+#endif
#include <part.h>
#include <flash.h>
ulong get_OPB_freq (void);
ulong get_PCI_freq (void);
#endif
-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \
- defined(CONFIG_LH7A40X) || defined(CONFIG_S3C6400)
+#if defined(CONFIG_S3C24X0) || \
+ defined(CONFIG_LH7A40X) || \
+ defined(CONFIG_S3C6400)
ulong get_FCLK (void);
ulong get_HCLK (void);
ulong get_PCLK (void);
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
-#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
+#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Configuation settings for the Faraday A320 board.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/a320.h>
+
+/*-----------------------------------------------------------------------
+ * CPU and Board Configuration Options
+ */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*-----------------------------------------------------------------------
+ * Timer
+ */
+#define CONFIG_SYS_HZ 1000 /* timer ticks per second */
+
+/*-----------------------------------------------------------------------
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*-----------------------------------------------------------------------
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART */
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1 0x98200000
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_CLK 18432000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY 3
+
+/*-----------------------------------------------------------------------
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+
+/*-----------------------------------------------------------------------
+ * size in bytes reserved for initial data
+*/
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*-----------------------------------------------------------------------
+ * SDRAM controller configuration
+ */
+#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \
+ FTSDMC020_TP0_TRP(1) | \
+ FTSDMC020_TP0_TRCD(1) | \
+ FTSDMC020_TP0_TRF(3) | \
+ FTSDMC020_TP0_TWR(1) | \
+ FTSDMC020_TP0_TCL(2))
+
+#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \
+ FTSDMC020_TP1_INI_REFT(8) | \
+ FTSDMC020_TP1_REF_INTV(0x180))
+
+#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \
+ FTSDMC020_BANK_DDW_X16 | \
+ FTSDMC020_BANK_DSZ_256M | \
+ FTSDMC020_BANK_MBW_32 | \
+ FTSDMC020_BANK_SIZE_64M)
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+/*
+ * Load address and memory test area should agree with
+ * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x12000000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x13F00000
+
+/*-----------------------------------------------------------------------
+ * Static memory controller configuration
+ */
+
+#include <asm/arch/ftsmc020.h>
+
+#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
+ FTSMC020_BANK_SIZE_1M | \
+ FTSMC020_BANK_MBW_8)
+
+#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
+ FTSMC020_TPR_AST(3) | \
+ FTSMC020_TPR_CTW(3) | \
+ FTSMC020_TPR_ATI(0xf) | \
+ FTSMC020_TPR_AT2(3) | \
+ FTSMC020_TPR_WTC(3) | \
+ FTSMC020_TPR_AHT(3) | \
+ FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_BASE(PHYS_FLASH_2) | \
+ FTSMC020_BANK_SIZE_32M | \
+ FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \
+ FTSMC020_TPR_CTW(3) | \
+ FTSMC020_TPR_ATI(0xf) | \
+ FTSMC020_TPR_AT2(3) | \
+ FTSMC020_TPR_WTC(3) | \
+ FTSMC020_TPR_AHT(3) | \
+ FTSMC020_TPR_TRNA(0xf))
+
+#define CONFIG_SYS_FTSMC020_CONFIGS { \
+ { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
+ { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
+}
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* support JEDEC */
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_LEGACY_512Kx8
+
+#define PHYS_FLASH_1 0x00000000
+#define PHYS_FLASH_2 0x00400000
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
+
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR 0x00060000
+#define CONFIG_ENV_SIZE 0x20000
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com>
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_DA830_EVM
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ 24000000
+#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
+#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* memtest start addr */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) /* 16MB test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */
+#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+
+/*
+ * I2C EEPROM definitions for catalyst 24W256 EEPROM chip
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#endif
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_CS 3
+#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_CLE_MASK 0x10
+#define CONFIG_SYS_ALE_MASK 0x8
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define DEF_BOOTM ""
+#endif
+
+#ifdef CONFIG_USE_NOR
+#define CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ (64 << 10) /* 64KB */
+#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3)
+#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define PHYS_FLASH_SIZE (32 << 20) /* Flash size 32MB */
+#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
+#define CONFIG_SYS_FLASH_SPL_ACCESS
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE (16 << 10)
+#define CONFIG_ENV_OFFSET (256 << 10)
+#define CONFIG_ENV_SECT_SIZE 4096
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE
+#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED 50000000
+#define CONFIG_SYS_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#endif
+
+
+/*
+ * U-Boot general configuration
+ */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#undef CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "DA830-evm > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock/2 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND ""
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_EEPROM
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SAVEENV
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+ !defined(CONFIG_USE_NOR) && \
+ !defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE (16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_ENV
+#endif
+
+#ifdef CONFIG_USB_DA8XX
+#define CONFIG_CMD_USB /* include support for usb */
+#define CONFIG_CMD_STORAGE /* include support for usb */
+#define CONFIG_CMD_FAT /* include support for FAT/storage*/
+#define CONFIG_DOS_PARTITION /* include support for FAT/storage*/
+#endif
+
+#endif /* __CONFIG_H */
/* Hardware drivers */
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* DM9000 */
#define CONFIG_NET_MULTI 1
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_SYS_NAND_BASE 0xd8000000
#define CONFIG_JFFS2_NAND
#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/*
* SD/MMC
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
+/* DDR - I use Infineon DDR */
+#define CONFIG_OMAP3_INFINEON_DDR 1
+
/* OMITTED: single 1 Gbit MT29F1G NAND flash */
/*
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* Status LED */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED 1
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
-#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
+#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T 1 /* This is an ARM920T core */
-#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
-#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */
+#define CONFIG_ARM920T 1 /* This is an ARM920T core */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */
+#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000 /* SMDK2400 has 12 MHz input clock */
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
-#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
+#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */
#define CONFIG_ENABLE_MMU
#endif
-#define CONFIG_MEMORY_UPPER_CODE
-
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T 1 /* This is an arm920t CPU */
-#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
-#define CONFIG_TRAB 1 /* on a TRAB Board */
-#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
+#define CONFIG_ARM920T 1 /* This is an arm920t CPU */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */
+#define CONFIG_TRAB 1 /* on a TRAB Board */
+#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
/* automatic software updates (see board/trab/auto_update.c) */
#define CONFIG_AUTO_UPDATE 1
+++ /dev/null
-/*
- * (C) Copyright 2003
- * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME : s3c2400.h
- * Version : 31.3.2003
- *
- * Based on S3C2400X User's manual Rev 1.1
- ************************************************/
-
-#ifndef __S3C2400_H__
-#define __S3C2400_H__
-
-#define S3C24X0_UART_CHANNELS 2
-#define S3C24X0_SPI_CHANNELS 1
-#define PALETTE (0x14A00400) /* SJS */
-
-enum s3c24x0_uarts_nr {
- S3C24X0_UART0,
- S3C24X0_UART1,
-};
-
-/*S3C2400 device base addresses */
-#define S3C24X0_MEMCTL_BASE 0x14000000
-#define S3C24X0_USB_HOST_BASE 0x14200000
-#define S3C24X0_INTERRUPT_BASE 0x14400000
-#define S3C24X0_DMA_BASE 0x14600000
-#define S3C24X0_CLOCK_POWER_BASE 0x14800000
-#define S3C24X0_LCD_BASE 0x14A00000
-#define S3C24X0_UART_BASE 0x15000000
-#define S3C24X0_TIMER_BASE 0x15100000
-#define S3C24X0_USB_DEVICE_BASE 0x15200140
-#define S3C24X0_WATCHDOG_BASE 0x15300000
-#define S3C24X0_I2C_BASE 0x15400000
-#define S3C24X0_I2S_BASE 0x15508000
-#define S3C24X0_GPIO_BASE 0x15600000
-#define S3C24X0_RTC_BASE 0x15700000
-#define S3C24X0_ADC_BASE 0x15800000
-#define S3C24X0_SPI_BASE 0x15900000
-#define S3C2400_MMC_BASE 0x15A00000
-
-/* include common stuff */
-#include <s3c24x0.h>
-
-
-static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
-{
- return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
-}
-static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
-{
- return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
-}
-static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
-{
- return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
-}
-static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
-{
- return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
-}
-static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
-{
- return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
-}
-static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
-{
- return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
-}
-static inline struct s3c24x0_uart
- *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
-{
- return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
-}
-static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
-{
- return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
-}
-static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
-{
- return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
-}
-static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
-{
- return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
-}
-static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
-{
- return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
-}
-static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
-{
- return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
-}
-static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
-{
- return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
-}
-static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
-{
- return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
-}
-static inline struct s3c2400_adc *s3c2400_get_base_adc(void)
-{
- return (struct s3c2400_adc *)S3C24X0_ADC_BASE;
-}
-static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
-{
- return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
-}
-static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void)
-{
- return (struct s3c2400_mmc *)S3C2400_MMC_BASE;
-}
-
-#endif /*__S3C2400_H__*/
+++ /dev/null
-/*
- * (C) Copyright 2003
- * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME : s3c2410.h
- * Version : 31.3.2003
- *
- * Based on S3C2410X User's manual Rev 1.1
- ************************************************/
-
-#ifndef __S3C2410_H__
-#define __S3C2410_H__
-
-#define S3C24X0_UART_CHANNELS 3
-#define S3C24X0_SPI_CHANNELS 2
-
-/* S3C2410 only supports 512 Byte HW ECC */
-#define S3C2410_ECCSIZE 512
-#define S3C2410_ECCBYTES 3
-
-enum s3c24x0_uarts_nr {
- S3C24X0_UART0,
- S3C24X0_UART1,
- S3C24X0_UART2
-};
-
-/* S3C2410 device base addresses */
-#define S3C24X0_MEMCTL_BASE 0x48000000
-#define S3C24X0_USB_HOST_BASE 0x49000000
-#define S3C24X0_INTERRUPT_BASE 0x4A000000
-#define S3C24X0_DMA_BASE 0x4B000000
-#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
-#define S3C24X0_LCD_BASE 0x4D000000
-#define S3C2410_NAND_BASE 0x4E000000
-#define S3C24X0_UART_BASE 0x50000000
-#define S3C24X0_TIMER_BASE 0x51000000
-#define S3C24X0_USB_DEVICE_BASE 0x52000140
-#define S3C24X0_WATCHDOG_BASE 0x53000000
-#define S3C24X0_I2C_BASE 0x54000000
-#define S3C24X0_I2S_BASE 0x55000000
-#define S3C24X0_GPIO_BASE 0x56000000
-#define S3C24X0_RTC_BASE 0x57000000
-#define S3C2410_ADC_BASE 0x58000000
-#define S3C24X0_SPI_BASE 0x59000000
-#define S3C2410_SDI_BASE 0x5A000000
-
-
-/* include common stuff */
-#include <s3c24x0.h>
-
-
-static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
-{
- return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
-}
-static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
-{
- return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
-}
-static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
-{
- return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
-}
-static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
-{
- return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
-}
-static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
-{
- return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
-}
-static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
-{
- return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
-}
-static inline struct s3c2410_nand *s3c2410_get_base_nand(void)
-{
- return (struct s3c2410_nand *)S3C2410_NAND_BASE;
-}
-static inline struct s3c24x0_uart
- *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
-{
- return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
-}
-static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
-{
- return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
-}
-static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
-{
- return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
-}
-static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
-{
- return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
-}
-static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
-{
- return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
-}
-static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
-{
- return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
-}
-static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
-{
- return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
-}
-static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
-{
- return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
-}
-static inline struct s3c2410_adc *s3c2410_get_base_adc(void)
-{
- return (struct s3c2410_adc *)S3C2410_ADC_BASE;
-}
-static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
-{
- return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
-}
-static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void)
-{
- return (struct s3c2410_sdi *)S3C2410_SDI_BASE;
-}
-
-#endif /*__S3C2410_H__*/
+++ /dev/null
-/*
- * (C) Copyright 2003
- * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME : s3c24x0.h
- * Version : 31.3.2003
- *
- * common stuff for SAMSUNG S3C24X0 SoC
- ************************************************/
-
-#ifndef __S3C24X0_H__
-#define __S3C24X0_H__
-
-typedef volatile u8 S3C24X0_REG8;
-typedef volatile u16 S3C24X0_REG16;
-typedef volatile u32 S3C24X0_REG32;
-
-/* Memory controller (see manual chapter 5) */
-struct s3c24x0_memctl {
- S3C24X0_REG32 BWSCON;
- S3C24X0_REG32 BANKCON[8];
- S3C24X0_REG32 REFRESH;
- S3C24X0_REG32 BANKSIZE;
- S3C24X0_REG32 MRSRB6;
- S3C24X0_REG32 MRSRB7;
-};
-
-
-/* USB HOST (see manual chapter 12) */
-struct s3c24x0_usb_host {
- S3C24X0_REG32 HcRevision;
- S3C24X0_REG32 HcControl;
- S3C24X0_REG32 HcCommonStatus;
- S3C24X0_REG32 HcInterruptStatus;
- S3C24X0_REG32 HcInterruptEnable;
- S3C24X0_REG32 HcInterruptDisable;
- S3C24X0_REG32 HcHCCA;
- S3C24X0_REG32 HcPeriodCuttendED;
- S3C24X0_REG32 HcControlHeadED;
- S3C24X0_REG32 HcControlCurrentED;
- S3C24X0_REG32 HcBulkHeadED;
- S3C24X0_REG32 HcBuldCurrentED;
- S3C24X0_REG32 HcDoneHead;
- S3C24X0_REG32 HcRmInterval;
- S3C24X0_REG32 HcFmRemaining;
- S3C24X0_REG32 HcFmNumber;
- S3C24X0_REG32 HcPeriodicStart;
- S3C24X0_REG32 HcLSThreshold;
- S3C24X0_REG32 HcRhDescriptorA;
- S3C24X0_REG32 HcRhDescriptorB;
- S3C24X0_REG32 HcRhStatus;
- S3C24X0_REG32 HcRhPortStatus1;
- S3C24X0_REG32 HcRhPortStatus2;
-};
-
-
-/* INTERRUPT (see manual chapter 14) */
-struct s3c24x0_interrupt {
- S3C24X0_REG32 SRCPND;
- S3C24X0_REG32 INTMOD;
- S3C24X0_REG32 INTMSK;
- S3C24X0_REG32 PRIORITY;
- S3C24X0_REG32 INTPND;
- S3C24X0_REG32 INTOFFSET;
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 SUBSRCPND;
- S3C24X0_REG32 INTSUBMSK;
-#endif
-};
-
-
-/* DMAS (see manual chapter 8) */
-struct s3c24x0_dma {
- S3C24X0_REG32 DISRC;
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 DISRCC;
-#endif
- S3C24X0_REG32 DIDST;
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 DIDSTC;
-#endif
- S3C24X0_REG32 DCON;
- S3C24X0_REG32 DSTAT;
- S3C24X0_REG32 DCSRC;
- S3C24X0_REG32 DCDST;
- S3C24X0_REG32 DMASKTRIG;
-#ifdef CONFIG_S3C2400
- S3C24X0_REG32 res[1];
-#endif
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 res[7];
-#endif
-};
-
-struct s3c24x0_dmas {
- struct s3c24x0_dma dma[4];
-};
-
-
-/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
-/* (see S3C2410 manual chapter 7) */
-struct s3c24x0_clock_power {
- S3C24X0_REG32 LOCKTIME;
- S3C24X0_REG32 MPLLCON;
- S3C24X0_REG32 UPLLCON;
- S3C24X0_REG32 CLKCON;
- S3C24X0_REG32 CLKSLOW;
- S3C24X0_REG32 CLKDIVN;
-};
-
-
-/* LCD CONTROLLER (see manual chapter 15) */
-struct s3c24x0_lcd {
- S3C24X0_REG32 LCDCON1;
- S3C24X0_REG32 LCDCON2;
- S3C24X0_REG32 LCDCON3;
- S3C24X0_REG32 LCDCON4;
- S3C24X0_REG32 LCDCON5;
- S3C24X0_REG32 LCDSADDR1;
- S3C24X0_REG32 LCDSADDR2;
- S3C24X0_REG32 LCDSADDR3;
- S3C24X0_REG32 REDLUT;
- S3C24X0_REG32 GREENLUT;
- S3C24X0_REG32 BLUELUT;
- S3C24X0_REG32 res[8];
- S3C24X0_REG32 DITHMODE;
- S3C24X0_REG32 TPAL;
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 LCDINTPND;
- S3C24X0_REG32 LCDSRCPND;
- S3C24X0_REG32 LCDINTMSK;
- S3C24X0_REG32 LPCSEL;
-#endif
-};
-
-
-/* NAND FLASH (see S3C2410 manual chapter 6) */
-struct s3c2410_nand {
- S3C24X0_REG32 NFCONF;
- S3C24X0_REG32 NFCMD;
- S3C24X0_REG32 NFADDR;
- S3C24X0_REG32 NFDATA;
- S3C24X0_REG32 NFSTAT;
- S3C24X0_REG32 NFECC;
-};
-
-
-/* UART (see manual chapter 11) */
-struct s3c24x0_uart {
- S3C24X0_REG32 ULCON;
- S3C24X0_REG32 UCON;
- S3C24X0_REG32 UFCON;
- S3C24X0_REG32 UMCON;
- S3C24X0_REG32 UTRSTAT;
- S3C24X0_REG32 UERSTAT;
- S3C24X0_REG32 UFSTAT;
- S3C24X0_REG32 UMSTAT;
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 UTXH;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 URXH;
-#else /* Little Endian */
- S3C24X0_REG8 UTXH;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 URXH;
- S3C24X0_REG8 res2[3];
-#endif
- S3C24X0_REG32 UBRDIV;
-};
-
-
-/* PWM TIMER (see manual chapter 10) */
-struct s3c24x0_timer {
- S3C24X0_REG32 TCNTB;
- S3C24X0_REG32 TCMPB;
- S3C24X0_REG32 TCNTO;
-};
-
-struct s3c24x0_timers {
- S3C24X0_REG32 TCFG0;
- S3C24X0_REG32 TCFG1;
- S3C24X0_REG32 TCON;
- struct s3c24x0_timer ch[4];
- S3C24X0_REG32 TCNTB4;
- S3C24X0_REG32 TCNTO4;
-};
-
-
-/* USB DEVICE (see manual chapter 13) */
-struct s3c24x0_usb_dev_fifos {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res[3];
- S3C24X0_REG8 EP_FIFO_REG;
-#else /* little endian */
- S3C24X0_REG8 EP_FIFO_REG;
- S3C24X0_REG8 res[3];
-#endif
-};
-
-struct s3c24x0_usb_dev_dmas {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 EP_DMA_CON;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 EP_DMA_UNIT;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 EP_DMA_FIFO;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 EP_DMA_TTC_L;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 EP_DMA_TTC_M;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 EP_DMA_TTC_H;
-#else /* little endian */
- S3C24X0_REG8 EP_DMA_CON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 EP_DMA_UNIT;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 EP_DMA_FIFO;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 EP_DMA_TTC_L;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 EP_DMA_TTC_M;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 EP_DMA_TTC_H;
- S3C24X0_REG8 res6[3];
-#endif
-};
-
-struct s3c24x0_usb_device {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 FUNC_ADDR_REG;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 PWR_REG;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 EP_INT_REG;
- S3C24X0_REG8 res4[15];
- S3C24X0_REG8 USB_INT_REG;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 EP_INT_EN_REG;
- S3C24X0_REG8 res6[15];
- S3C24X0_REG8 USB_INT_EN_REG;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 FRAME_NUM1_REG;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 FRAME_NUM2_REG;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 INDEX_REG;
- S3C24X0_REG8 res10[7];
- S3C24X0_REG8 MAXP_REG;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 IN_CSR2_REG;
- S3C24X0_REG8 res13[7];
- S3C24X0_REG8 OUT_CSR1_REG;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 OUT_CSR2_REG;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 OUT_FIFO_CNT1_REG;
- S3C24X0_REG8 res16[3];
- S3C24X0_REG8 OUT_FIFO_CNT2_REG;
-#else /* little endian */
- S3C24X0_REG8 FUNC_ADDR_REG;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 PWR_REG;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 EP_INT_REG;
- S3C24X0_REG8 res3[15];
- S3C24X0_REG8 USB_INT_REG;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 EP_INT_EN_REG;
- S3C24X0_REG8 res5[15];
- S3C24X0_REG8 USB_INT_EN_REG;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 FRAME_NUM1_REG;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 FRAME_NUM2_REG;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 INDEX_REG;
- S3C24X0_REG8 res9[7];
- S3C24X0_REG8 MAXP_REG;
- S3C24X0_REG8 res10[7];
- S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 IN_CSR2_REG;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 OUT_CSR1_REG;
- S3C24X0_REG8 res13[7];
- S3C24X0_REG8 OUT_CSR2_REG;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 OUT_FIFO_CNT1_REG;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 OUT_FIFO_CNT2_REG;
- S3C24X0_REG8 res16[3];
-#endif /* __BIG_ENDIAN */
- struct s3c24x0_usb_dev_fifos fifo[5];
- struct s3c24x0_usb_dev_dmas dma[5];
-};
-
-
-/* WATCH DOG TIMER (see manual chapter 18) */
-struct s3c24x0_watchdog {
- S3C24X0_REG32 WTCON;
- S3C24X0_REG32 WTDAT;
- S3C24X0_REG32 WTCNT;
-};
-
-
-/* IIC (see manual chapter 20) */
-struct s3c24x0_i2c {
- S3C24X0_REG32 IICCON;
- S3C24X0_REG32 IICSTAT;
- S3C24X0_REG32 IICADD;
- S3C24X0_REG32 IICDS;
-};
-
-
-/* IIS (see manual chapter 21) */
-struct s3c24x0_i2s {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG16 res1;
- S3C24X0_REG16 IISCON;
- S3C24X0_REG16 res2;
- S3C24X0_REG16 IISMOD;
- S3C24X0_REG16 res3;
- S3C24X0_REG16 IISPSR;
- S3C24X0_REG16 res4;
- S3C24X0_REG16 IISFCON;
- S3C24X0_REG16 res5;
- S3C24X0_REG16 IISFIFO;
-#else /* little endian */
- S3C24X0_REG16 IISCON;
- S3C24X0_REG16 res1;
- S3C24X0_REG16 IISMOD;
- S3C24X0_REG16 res2;
- S3C24X0_REG16 IISPSR;
- S3C24X0_REG16 res3;
- S3C24X0_REG16 IISFCON;
- S3C24X0_REG16 res4;
- S3C24X0_REG16 IISFIFO;
- S3C24X0_REG16 res5;
-#endif
-};
-
-
-/* I/O PORT (see manual chapter 9) */
-struct s3c24x0_gpio {
-#ifdef CONFIG_S3C2400
- S3C24X0_REG32 PACON;
- S3C24X0_REG32 PADAT;
-
- S3C24X0_REG32 PBCON;
- S3C24X0_REG32 PBDAT;
- S3C24X0_REG32 PBUP;
-
- S3C24X0_REG32 PCCON;
- S3C24X0_REG32 PCDAT;
- S3C24X0_REG32 PCUP;
-
- S3C24X0_REG32 PDCON;
- S3C24X0_REG32 PDDAT;
- S3C24X0_REG32 PDUP;
-
- S3C24X0_REG32 PECON;
- S3C24X0_REG32 PEDAT;
- S3C24X0_REG32 PEUP;
-
- S3C24X0_REG32 PFCON;
- S3C24X0_REG32 PFDAT;
- S3C24X0_REG32 PFUP;
-
- S3C24X0_REG32 PGCON;
- S3C24X0_REG32 PGDAT;
- S3C24X0_REG32 PGUP;
-
- S3C24X0_REG32 OPENCR;
-
- S3C24X0_REG32 MISCCR;
- S3C24X0_REG32 EXTINT;
-#endif
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 GPACON;
- S3C24X0_REG32 GPADAT;
- S3C24X0_REG32 res1[2];
- S3C24X0_REG32 GPBCON;
- S3C24X0_REG32 GPBDAT;
- S3C24X0_REG32 GPBUP;
- S3C24X0_REG32 res2;
- S3C24X0_REG32 GPCCON;
- S3C24X0_REG32 GPCDAT;
- S3C24X0_REG32 GPCUP;
- S3C24X0_REG32 res3;
- S3C24X0_REG32 GPDCON;
- S3C24X0_REG32 GPDDAT;
- S3C24X0_REG32 GPDUP;
- S3C24X0_REG32 res4;
- S3C24X0_REG32 GPECON;
- S3C24X0_REG32 GPEDAT;
- S3C24X0_REG32 GPEUP;
- S3C24X0_REG32 res5;
- S3C24X0_REG32 GPFCON;
- S3C24X0_REG32 GPFDAT;
- S3C24X0_REG32 GPFUP;
- S3C24X0_REG32 res6;
- S3C24X0_REG32 GPGCON;
- S3C24X0_REG32 GPGDAT;
- S3C24X0_REG32 GPGUP;
- S3C24X0_REG32 res7;
- S3C24X0_REG32 GPHCON;
- S3C24X0_REG32 GPHDAT;
- S3C24X0_REG32 GPHUP;
- S3C24X0_REG32 res8;
-
- S3C24X0_REG32 MISCCR;
- S3C24X0_REG32 DCLKCON;
- S3C24X0_REG32 EXTINT0;
- S3C24X0_REG32 EXTINT1;
- S3C24X0_REG32 EXTINT2;
- S3C24X0_REG32 EINTFLT0;
- S3C24X0_REG32 EINTFLT1;
- S3C24X0_REG32 EINTFLT2;
- S3C24X0_REG32 EINTFLT3;
- S3C24X0_REG32 EINTMASK;
- S3C24X0_REG32 EINTPEND;
- S3C24X0_REG32 GSTATUS0;
- S3C24X0_REG32 GSTATUS1;
- S3C24X0_REG32 GSTATUS2;
- S3C24X0_REG32 GSTATUS3;
- S3C24X0_REG32 GSTATUS4;
-#endif
-};
-
-
-/* RTC (see manual chapter 17) */
-struct s3c24x0_rtc {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[67];
- S3C24X0_REG8 RTCCON;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 TICNT;
- S3C24X0_REG8 res3[11];
- S3C24X0_REG8 RTCALM;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 ALMSEC;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 ALMMIN;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 ALMHOUR;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 ALMDATE;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 ALMMON;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 ALMYEAR;
- S3C24X0_REG8 res10[3];
- S3C24X0_REG8 RTCRST;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 BCDSEC;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 BCDMIN;
- S3C24X0_REG8 res13[3];
- S3C24X0_REG8 BCDHOUR;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 BCDDATE;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 BCDDAY;
- S3C24X0_REG8 res16[3];
- S3C24X0_REG8 BCDMON;
- S3C24X0_REG8 res17[3];
- S3C24X0_REG8 BCDYEAR;
-#else /* little endian */
- S3C24X0_REG8 res0[64];
- S3C24X0_REG8 RTCCON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 TICNT;
- S3C24X0_REG8 res2[11];
- S3C24X0_REG8 RTCALM;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 ALMSEC;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 ALMMIN;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 ALMHOUR;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 ALMDATE;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 ALMMON;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 ALMYEAR;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 RTCRST;
- S3C24X0_REG8 res10[3];
- S3C24X0_REG8 BCDSEC;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 BCDMIN;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 BCDHOUR;
- S3C24X0_REG8 res13[3];
- S3C24X0_REG8 BCDDATE;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 BCDDAY;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 BCDMON;
- S3C24X0_REG8 res16[3];
- S3C24X0_REG8 BCDYEAR;
- S3C24X0_REG8 res17[3];
-#endif
-};
-
-
-/* ADC (see manual chapter 16) */
-struct s3c2400_adc {
- S3C24X0_REG32 ADCCON;
- S3C24X0_REG32 ADCDAT;
-};
-
-
-/* ADC (see manual chapter 16) */
-struct s3c2410_adc {
- S3C24X0_REG32 ADCCON;
- S3C24X0_REG32 ADCTSC;
- S3C24X0_REG32 ADCDLY;
- S3C24X0_REG32 ADCDAT0;
- S3C24X0_REG32 ADCDAT1;
-};
-
-
-/* SPI (see manual chapter 22) */
-struct s3c24x0_spi_channel {
- S3C24X0_REG8 SPCON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 SPSTA;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 SPPIN;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 SPPRE;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 SPTDAT;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 SPRDAT;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 res7[16];
-};
-
-struct s3c24x0_spi {
- struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS];
-};
-
-
-/* MMC INTERFACE (see S3C2400 manual chapter 19) */
-struct s3c2400_mmc {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 MMCON;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 MMCRR;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 MMFCON;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 MMSTA;
- S3C24X0_REG16 res5;
- S3C24X0_REG16 MMFSTA;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 MMPRE;
- S3C24X0_REG16 res7;
- S3C24X0_REG16 MMLEN;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 MMCR7;
- S3C24X0_REG32 MMRSP[4];
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 MMCMD0;
- S3C24X0_REG32 MMCMD1;
- S3C24X0_REG16 res10;
- S3C24X0_REG16 MMCR16;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 MMDAT;
-#else
- S3C24X0_REG8 MMCON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 MMCRR;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 MMFCON;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 MMSTA;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG16 MMFSTA;
- S3C24X0_REG16 res5;
- S3C24X0_REG8 MMPRE;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG16 MMLEN;
- S3C24X0_REG16 res7;
- S3C24X0_REG8 MMCR7;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG32 MMRSP[4];
- S3C24X0_REG8 MMCMD0;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG32 MMCMD1;
- S3C24X0_REG16 MMCR16;
- S3C24X0_REG16 res10;
- S3C24X0_REG8 MMDAT;
- S3C24X0_REG8 res11[3];
-#endif
-};
-
-
-/* SD INTERFACE (see S3C2410 manual chapter 19) */
-struct s3c2410_sdi {
- S3C24X0_REG32 SDICON;
- S3C24X0_REG32 SDIPRE;
- S3C24X0_REG32 SDICARG;
- S3C24X0_REG32 SDICCON;
- S3C24X0_REG32 SDICSTA;
- S3C24X0_REG32 SDIRSP0;
- S3C24X0_REG32 SDIRSP1;
- S3C24X0_REG32 SDIRSP2;
- S3C24X0_REG32 SDIRSP3;
- S3C24X0_REG32 SDIDTIMER;
- S3C24X0_REG32 SDIBSIZE;
- S3C24X0_REG32 SDIDCON;
- S3C24X0_REG32 SDIDCNT;
- S3C24X0_REG32 SDIDSTA;
- S3C24X0_REG32 SDIFSTA;
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res[3];
- S3C24X0_REG8 SDIDAT;
-#else
- S3C24X0_REG8 SDIDAT;
- S3C24X0_REG8 res[3];
-#endif
- S3C24X0_REG32 SDIIMSK;
-};
-
-#endif /*__S3C24X0_H__*/
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com.
- * - only support for S3C6400
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME : s3c6400.h
- *
- * Based on S3C6400 User's manual Rev 0.0
- ************************************************/
-
-#ifndef __S3C6400_H__
-#define __S3C6400_H__
-
-#define S3C64XX_UART_CHANNELS 3
-#define S3C64XX_SPI_CHANNELS 2
-
-#include <asm/hardware.h>
-
-#define ELFIN_CLOCK_POWER_BASE 0x7e00f000
-
-/* Clock & Power Controller for mDirac3*/
-#define APLL_LOCK_OFFSET 0x00
-#define MPLL_LOCK_OFFSET 0x04
-#define EPLL_LOCK_OFFSET 0x08
-#define APLL_CON_OFFSET 0x0C
-#define MPLL_CON_OFFSET 0x10
-#define EPLL_CON0_OFFSET 0x14
-#define EPLL_CON1_OFFSET 0x18
-#define CLK_SRC_OFFSET 0x1C
-#define CLK_DIV0_OFFSET 0x20
-#define CLK_DIV1_OFFSET 0x24
-#define CLK_DIV2_OFFSET 0x28
-#define CLK_OUT_OFFSET 0x2C
-#define HCLK_GATE_OFFSET 0x30
-#define PCLK_GATE_OFFSET 0x34
-#define SCLK_GATE_OFFSET 0x38
-#define AHB_CON0_OFFSET 0x100
-#define AHB_CON1_OFFSET 0x104
-#define AHB_CON2_OFFSET 0x108
-#define SELECT_DMA_OFFSET 0x110
-#define SW_RST_OFFSET 0x114
-#define SYS_ID_OFFSET 0x118
-#define MEM_SYS_CFG_OFFSET 0x120
-#define QOS_OVERRIDE0_OFFSET 0x124
-#define QOS_OVERRIDE1_OFFSET 0x128
-#define MEM_CFG_STAT_OFFSET 0x12C
-#define PWR_CFG_OFFSET 0x804
-#define EINT_MASK_OFFSET 0x808
-#define NOR_CFG_OFFSET 0x810
-#define STOP_CFG_OFFSET 0x814
-#define SLEEP_CFG_OFFSET 0x818
-#define OSC_FREQ_OFFSET 0x820
-#define OSC_STABLE_OFFSET 0x824
-#define PWR_STABLE_OFFSET 0x828
-#define FPC_STABLE_OFFSET 0x82C
-#define MTC_STABLE_OFFSET 0x830
-#define OTHERS_OFFSET 0x900
-#define RST_STAT_OFFSET 0x904
-#define WAKEUP_STAT_OFFSET 0x908
-#define BLK_PWR_STAT_OFFSET 0x90C
-#define INF_REG0_OFFSET 0xA00
-#define INF_REG1_OFFSET 0xA04
-#define INF_REG2_OFFSET 0xA08
-#define INF_REG3_OFFSET 0xA0C
-#define INF_REG4_OFFSET 0xA10
-#define INF_REG5_OFFSET 0xA14
-#define INF_REG6_OFFSET 0xA18
-#define INF_REG7_OFFSET 0xA1C
-
-#define OSC_CNT_VAL_OFFSET 0x824
-#define PWR_CNT_VAL_OFFSET 0x828
-#define FPC_CNT_VAL_OFFSET 0x82C
-#define MTC_CNT_VAL_OFFSET 0x830
-
-#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
-#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
-#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
-#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
-#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
-#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
-#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
-#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
-#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
-#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
-#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
-#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
-#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
-#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
-#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
-#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
-#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
-#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
-#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- SELECT_DMA_OFFSET)
-#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
-#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
-#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- MEM_SYS_CFG_OFFSET)
-#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- QOS_OVERRIDE0_OFFSET)
-#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- QOS_OVERRIDE1_OFFSET)
-#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- MEM_CFG_STAT_OFFSET)
-#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
-#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
-#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
-#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
-#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
-#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
-#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- OSC_CNT_VAL_OFFSET)
-#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- PWR_CNT_VAL_OFFSET)
-#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- FPC_CNT_VAL_OFFSET)
-#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- MTC_CNT_VAL_OFFSET)
-#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
-#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
-#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- WAKEUP_STAT_OFFSET)
-#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- BLK_PWR_STAT_OFFSET)
-#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
-#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
-#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
-#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
-#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
-#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
-#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
-#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
-
-#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
-#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
-#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
-#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
-#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
-#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
-#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
-#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
-#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
-#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
-#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
-#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
-#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
-#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
-#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
-#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
-#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
-#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
-#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET)
-#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
-#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
-#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET)
-#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET)
-#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET)
-#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET)
-#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
-#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
-#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
-#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
-#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
-#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
-#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET)
-#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET)
-#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET)
-#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET)
-#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
-#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
-#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
-#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET)
-#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
-#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
-#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
-#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
-#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
-#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
-#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
-#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
-
-
-/*
- * GPIO
- */
-#define ELFIN_GPIO_BASE 0x7f008000
-
-#define GPACON_OFFSET 0x00
-#define GPADAT_OFFSET 0x04
-#define GPAPUD_OFFSET 0x08
-#define GPACONSLP_OFFSET 0x0C
-#define GPAPUDSLP_OFFSET 0x10
-#define GPBCON_OFFSET 0x20
-#define GPBDAT_OFFSET 0x24
-#define GPBPUD_OFFSET 0x28
-#define GPBCONSLP_OFFSET 0x2C
-#define GPBPUDSLP_OFFSET 0x30
-#define GPCCON_OFFSET 0x40
-#define GPCDAT_OFFSET 0x44
-#define GPCPUD_OFFSET 0x48
-#define GPCCONSLP_OFFSET 0x4C
-#define GPCPUDSLP_OFFSET 0x50
-#define GPDCON_OFFSET 0x60
-#define GPDDAT_OFFSET 0x64
-#define GPDPUD_OFFSET 0x68
-#define GPDCONSLP_OFFSET 0x6C
-#define GPDPUDSLP_OFFSET 0x70
-#define GPECON_OFFSET 0x80
-#define GPEDAT_OFFSET 0x84
-#define GPEPUD_OFFSET 0x88
-#define GPECONSLP_OFFSET 0x8C
-#define GPEPUDSLP_OFFSET 0x90
-#define GPFCON_OFFSET 0xA0
-#define GPFDAT_OFFSET 0xA4
-#define GPFPUD_OFFSET 0xA8
-#define GPFCONSLP_OFFSET 0xAC
-#define GPFPUDSLP_OFFSET 0xB0
-#define GPGCON_OFFSET 0xC0
-#define GPGDAT_OFFSET 0xC4
-#define GPGPUD_OFFSET 0xC8
-#define GPGCONSLP_OFFSET 0xCC
-#define GPGPUDSLP_OFFSET 0xD0
-#define GPHCON0_OFFSET 0xE0
-#define GPHCON1_OFFSET 0xE4
-#define GPHDAT_OFFSET 0xE8
-#define GPHPUD_OFFSET 0xEC
-#define GPHCONSLP_OFFSET 0xF0
-#define GPHPUDSLP_OFFSET 0xF4
-#define GPICON_OFFSET 0x100
-#define GPIDAT_OFFSET 0x104
-#define GPIPUD_OFFSET 0x108
-#define GPICONSLP_OFFSET 0x10C
-#define GPIPUDSLP_OFFSET 0x110
-#define GPJCON_OFFSET 0x120
-#define GPJDAT_OFFSET 0x124
-#define GPJPUD_OFFSET 0x128
-#define GPJCONSLP_OFFSET 0x12C
-#define GPJPUDSLP_OFFSET 0x130
-#define MEM0DRVCON_OFFSET 0x1D0
-#define MEM1DRVCON_OFFSET 0x1D4
-#define GPKCON0_OFFSET 0x800
-#define GPKCON1_OFFSET 0x804
-#define GPKDAT_OFFSET 0x808
-#define GPKPUD_OFFSET 0x80C
-#define GPLCON0_OFFSET 0x810
-#define GPLCON1_OFFSET 0x814
-#define GPLDAT_OFFSET 0x818
-#define GPLPUD_OFFSET 0x81C
-#define GPMCON_OFFSET 0x820
-#define GPMDAT_OFFSET 0x824
-#define GPMPUD_OFFSET 0x828
-#define GPNCON_OFFSET 0x830
-#define GPNDAT_OFFSET 0x834
-#define GPNPUD_OFFSET 0x838
-#define GPOCON_OFFSET 0x140
-#define GPODAT_OFFSET 0x144
-#define GPOPUD_OFFSET 0x148
-#define GPOCONSLP_OFFSET 0x14C
-#define GPOPUDSLP_OFFSET 0x150
-#define GPPCON_OFFSET 0x160
-#define GPPDAT_OFFSET 0x164
-#define GPPPUD_OFFSET 0x168
-#define GPPCONSLP_OFFSET 0x16C
-#define GPPPUDSLP_OFFSET 0x170
-#define GPQCON_OFFSET 0x180
-#define GPQDAT_OFFSET 0x184
-#define GPQPUD_OFFSET 0x188
-#define GPQCONSLP_OFFSET 0x18C
-#define GPQPUDSLP_OFFSET 0x190
-
-#define EINTPEND_OFFSET 0x924
-
-#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET)
-#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET)
-#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET)
-#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
-#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
-#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET)
-#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET)
-#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET)
-#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
-#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
-#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET)
-#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET)
-#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET)
-#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
-#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
-#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET)
-#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET)
-#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET)
-#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
-#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
-#define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET)
-#define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET)
-#define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET)
-#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
-#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
-#define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET)
-#define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET)
-#define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET)
-#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
-#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
-#define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET)
-#define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET)
-#define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET)
-#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
-#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
-#define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET)
-#define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET)
-#define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET)
-#define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET)
-#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
-#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
-#define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET)
-#define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET)
-#define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET)
-#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
-#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
-#define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET)
-#define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET)
-#define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET)
-#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
-#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
-#define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
-#define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET)
-#define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET)
-#define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET)
-#define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET)
-#define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET)
-#define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET)
-#define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET)
-#define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET)
-#define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET)
-#define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET)
-#define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET)
-#define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET)
-#define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET)
-#define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET)
-#define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET)
-#define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET)
-#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
-#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
-#define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET)
-#define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET)
-#define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET)
-#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
-#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
-#define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET)
-#define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET)
-#define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET)
-#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
-#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
-
-/*
- * Bus Matrix
- */
-#define ELFIN_MEM_SYS_CFG 0x7e00f120
-
-#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12)
-
-#define S3C64XX_MEM_SYS_CFG_NAND 0x0008
-#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT
-
-#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET)
-#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET)
-#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET)
-#define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
-#define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
-#define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET)
-#define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET)
-#define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET)
-#define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
-#define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
-#define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET)
-#define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET)
-#define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET)
-#define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
-#define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
-#define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET)
-#define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET)
-#define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET)
-#define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
-#define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
-#define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET)
-#define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET)
-#define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET)
-#define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
-#define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
-#define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET)
-#define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET)
-#define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET)
-#define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
-#define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
-#define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET)
-#define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET)
-#define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET)
-#define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
-#define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
-#define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET)
-#define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET)
-#define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET)
-#define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET)
-#define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
-#define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
-#define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET)
-#define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET)
-#define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET)
-#define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
-#define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
-#define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET)
-#define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET)
-#define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET)
-#define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
-#define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
-#define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET)
-#define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET)
-#define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET)
-#define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET)
-#define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET)
-#define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET)
-#define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET)
-#define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET)
-#define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET)
-#define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET)
-#define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET)
-#define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET)
-#define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET)
-#define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET)
-#define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET)
-#define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET)
-#define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET)
-#define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
-#define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
-#define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET)
-#define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET)
-#define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET)
-#define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
-#define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
-#define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET)
-#define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET)
-#define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET)
-#define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
-#define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
-
-/*
- * Memory controller
- */
-#define ELFIN_SROM_BASE 0x70000000
-
-#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0)
-#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4)
-#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8)
-#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC)
-#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10)
-#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14)
-#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18)
-
-/*
- * SDRAM Controller
- */
-#define ELFIN_DMC0_BASE 0x7e000000
-#define ELFIN_DMC1_BASE 0x7e001000
-
-#define INDEX_DMC_MEMC_STATUS 0x00
-#define INDEX_DMC_MEMC_CMD 0x04
-#define INDEX_DMC_DIRECT_CMD 0x08
-#define INDEX_DMC_MEMORY_CFG 0x0C
-#define INDEX_DMC_REFRESH_PRD 0x10
-#define INDEX_DMC_CAS_LATENCY 0x14
-#define INDEX_DMC_T_DQSS 0x18
-#define INDEX_DMC_T_MRD 0x1C
-#define INDEX_DMC_T_RAS 0x20
-#define INDEX_DMC_T_RC 0x24
-#define INDEX_DMC_T_RCD 0x28
-#define INDEX_DMC_T_RFC 0x2C
-#define INDEX_DMC_T_RP 0x30
-#define INDEX_DMC_T_RRD 0x34
-#define INDEX_DMC_T_WR 0x38
-#define INDEX_DMC_T_WTR 0x3C
-#define INDEX_DMC_T_XP 0x40
-#define INDEX_DMC_T_XSR 0x44
-#define INDEX_DMC_T_ESR 0x48
-#define INDEX_DMC_MEMORY_CFG2 0x4C
-#define INDEX_DMC_CHIP_0_CFG 0x200
-#define INDEX_DMC_CHIP_1_CFG 0x204
-#define INDEX_DMC_CHIP_2_CFG 0x208
-#define INDEX_DMC_CHIP_3_CFG 0x20C
-#define INDEX_DMC_USER_STATUS 0x300
-#define INDEX_DMC_USER_CONFIG 0x304
-
-/*
- * Memory Chip direct command
- */
-#define DMC_NOP0 0x0c0000
-#define DMC_NOP1 0x1c0000
-#define DMC_PA0 0x000000 /* Precharge all */
-#define DMC_PA1 0x100000
-#define DMC_AR0 0x040000 /* Autorefresh */
-#define DMC_AR1 0x140000
-#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */
-#define DMC_SDR_MR1 0x180032
-#define DMC_DDR_MR0 0x080162
-#define DMC_DDR_MR1 0x180162
-#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */
-#define DMC_mDDR_MR1 0x180032
-#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */
-#define DMC_mSDR_EMR1 0x1a0000
-#define DMC_DDR_EMR0 0x090000
-#define DMC_DDR_EMR1 0x190000
-#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */
-#define DMC_mDDR_EMR1 0x1a0000
-
-/*
- * Definitions for memory configuration
- * Set memory configuration
- * active_chips = 1'b0 (1 chip)
- * qos_master_chip = 3'b000(ARID[3:0])
- * memory burst = 3'b010(burst 4)
- * stop_mem_clock = 1'b0(disable dynamical stop)
- * auto_power_down = 1'b0(disable auto power-down mode)
- * power_down_prd = 6'b00_0000(0 cycle for auto power-down)
- * ap_bit = 1'b0 (bit position of auto-precharge is 10)
- * row_bits = 3'b010(# row address 13)
- * column_bits = 3'b010(# column address 10 )
- *
- * Set user configuration
- * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR
- *
- * Set chip select for chip [n]
- * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff
- * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24]
- */
-
-/*
- * Nand flash controller
- */
-#define ELFIN_NAND_BASE 0x70200000
-
-#define NFCONF_OFFSET 0x00
-#define NFCONT_OFFSET 0x04
-#define NFCMMD_OFFSET 0x08
-#define NFADDR_OFFSET 0x0c
-#define NFDATA_OFFSET 0x10
-#define NFMECCDATA0_OFFSET 0x14
-#define NFMECCDATA1_OFFSET 0x18
-#define NFSECCDATA0_OFFSET 0x1c
-#define NFSBLK_OFFSET 0x20
-#define NFEBLK_OFFSET 0x24
-#define NFSTAT_OFFSET 0x28
-#define NFESTAT0_OFFSET 0x2c
-#define NFESTAT1_OFFSET 0x30
-#define NFMECC0_OFFSET 0x34
-#define NFMECC1_OFFSET 0x38
-#define NFSECC_OFFSET 0x3c
-#define NFMLCBITPT_OFFSET 0x40
-
-#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET)
-#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET)
-#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET)
-#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET)
-#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
-#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
-#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
-#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET)
-#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET)
-#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET)
-#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET)
-#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET)
-#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET)
-#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET)
-#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET)
-#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
-
-#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET)
-#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET)
-#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET)
-#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET)
-#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
-#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
-#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
-#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET)
-#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET)
-#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET)
-#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET)
-#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET)
-#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET)
-#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET)
-#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET)
-#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
-
-#define NFCONF_ECC_4BIT (1<<24)
-
-#define NFCONT_ECC_ENC (1<<18)
-#define NFCONT_WP (1<<16)
-#define NFCONT_MECCLOCK (1<<7)
-#define NFCONT_SECCLOCK (1<<6)
-#define NFCONT_INITMECC (1<<5)
-#define NFCONT_INITSECC (1<<4)
-#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC)
-#define NFCONT_CS_ALT (1<<2)
-#define NFCONT_CS (1<<1)
-#define NFCONT_ENABLE (1<<0)
-
-#define NFSTAT_ECCENCDONE (1<<7)
-#define NFSTAT_ECCDECDONE (1<<6)
-#define NFSTAT_RnB (1<<0)
-
-#define NFESTAT0_ECCBUSY (1<<31)
-
-/*
- * Interrupt
- */
-#define ELFIN_VIC0_BASE_ADDR 0x71200000
-#define ELFIN_VIC1_BASE_ADDR 0x71300000
-#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */
-#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */
-#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */
-#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */
-#define oVECTADDR 0xF00 /* VIC ADDRESS */
-
-/*
- * Watchdog timer
- */
-#define ELFIN_WATCHDOG_BASE 0x7E004000
-
-#define WTCON_REG __REG(0x7E004004)
-#define WTDAT_REG __REG(0x7E004008)
-#define WTCNT_REG __REG(0x7E00400C)
-
-
-/*
- * UART
- */
-#define ELFIN_UART_BASE 0x7F005000
-
-#define ELFIN_UART0_OFFSET 0x0000
-#define ELFIN_UART1_OFFSET 0x0400
-#define ELFIN_UART2_OFFSET 0x0800
-
-#define ULCON_OFFSET 0x00
-#define UCON_OFFSET 0x04
-#define UFCON_OFFSET 0x08
-#define UMCON_OFFSET 0x0C
-#define UTRSTAT_OFFSET 0x10
-#define UERSTAT_OFFSET 0x14
-#define UFSTAT_OFFSET 0x18
-#define UMSTAT_OFFSET 0x1C
-#define UTXH_OFFSET 0x20
-#define URXH_OFFSET 0x24
-#define UBRDIV_OFFSET 0x28
-#define UDIVSLOT_OFFSET 0x2C
-#define UINTP_OFFSET 0x30
-#define UINTSP_OFFSET 0x34
-#define UINTM_OFFSET 0x38
-
-#define ULCON0_REG __REG(0x7F005000)
-#define UCON0_REG __REG(0x7F005004)
-#define UFCON0_REG __REG(0x7F005008)
-#define UMCON0_REG __REG(0x7F00500C)
-#define UTRSTAT0_REG __REG(0x7F005010)
-#define UERSTAT0_REG __REG(0x7F005014)
-#define UFSTAT0_REG __REG(0x7F005018)
-#define UMSTAT0_REG __REG(0x7F00501c)
-#define UTXH0_REG __REG(0x7F005020)
-#define URXH0_REG __REG(0x7F005024)
-#define UBRDIV0_REG __REG(0x7F005028)
-#define UDIVSLOT0_REG __REG(0x7F00502c)
-#define UINTP0_REG __REG(0x7F005030)
-#define UINTSP0_REG __REG(0x7F005034)
-#define UINTM0_REG __REG(0x7F005038)
-
-#define ULCON1_REG __REG(0x7F005400)
-#define UCON1_REG __REG(0x7F005404)
-#define UFCON1_REG __REG(0x7F005408)
-#define UMCON1_REG __REG(0x7F00540C)
-#define UTRSTAT1_REG __REG(0x7F005410)
-#define UERSTAT1_REG __REG(0x7F005414)
-#define UFSTAT1_REG __REG(0x7F005418)
-#define UMSTAT1_REG __REG(0x7F00541c)
-#define UTXH1_REG __REG(0x7F005420)
-#define URXH1_REG __REG(0x7F005424)
-#define UBRDIV1_REG __REG(0x7F005428)
-#define UDIVSLOT1_REG __REG(0x7F00542c)
-#define UINTP1_REG __REG(0x7F005430)
-#define UINTSP1_REG __REG(0x7F005434)
-#define UINTM1_REG __REG(0x7F005438)
-
-#define UTRSTAT_TX_EMPTY (1 << 2)
-#define UTRSTAT_RX_READY (1 << 0)
-#define UART_ERR_MASK 0xF
-
-/*
- * PWM timer
- */
-#define ELFIN_TIMER_BASE 0x7F006000
-
-#define TCFG0_REG __REG(0x7F006000)
-#define TCFG1_REG __REG(0x7F006004)
-#define TCON_REG __REG(0x7F006008)
-#define TCNTB0_REG __REG(0x7F00600c)
-#define TCMPB0_REG __REG(0x7F006010)
-#define TCNTO0_REG __REG(0x7F006014)
-#define TCNTB1_REG __REG(0x7F006018)
-#define TCMPB1_REG __REG(0x7F00601c)
-#define TCNTO1_REG __REG(0x7F006020)
-#define TCNTB2_REG __REG(0x7F006024)
-#define TCMPB2_REG __REG(0x7F006028)
-#define TCNTO2_REG __REG(0x7F00602c)
-#define TCNTB3_REG __REG(0x7F006030)
-#define TCMPB3_REG __REG(0x7F006034)
-#define TCNTO3_REG __REG(0x7F006038)
-#define TCNTB4_REG __REG(0x7F00603c)
-#define TCNTO4_REG __REG(0x7F006040)
-
-/* Fields */
-#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */
-#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */
-#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */
-#define fTCFG1_MUX4 Fld(4, 16)
-/* bits */
-#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE)
-#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1)
-#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0)
-#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */
-#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */
-#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */
-#define COUNT_4_ON (TCON_4_ONOFF * 1)
-#define COUNT_4_OFF (TCON_4_ONOFF * 0)
-#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */
-#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1)
-#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO)
-#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */
-#define TIMER3_IVT_ON (TCON_3_INVERT * 1)
-#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT))
-#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */
-#define TIMER3_MANUP (TCON_3_MAN*1)
-#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN))
-#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */
-#define TIMER3_ON (TCON_3_ONOFF * 1)
-#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF))
-
-#if defined(CONFIG_CLK_400_100_50)
-#define STARTUP_AMDIV 400
-#define STARTUP_MDIV 400
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#elif defined(CONFIG_CLK_400_133_66)
-#define STARTUP_AMDIV 400
-#define STARTUP_MDIV 533
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#elif defined(CONFIG_CLK_533_133_66)
-#define STARTUP_AMDIV 533
-#define STARTUP_MDIV 533
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#elif defined(CONFIG_CLK_667_133_66)
-#define STARTUP_AMDIV 667
-#define STARTUP_MDIV 533
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#endif
-
-#define STARTUP_PCLKDIV 3
-#define STARTUP_HCLKX2DIV 1
-#define STARTUP_HCLKDIV 1
-#define STARTUP_MPLLDIV 1
-#define STARTUP_APLLDIV 0
-
-#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \
- (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV)
-#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_MDIV)
-
-#if defined(CONFIG_SYNC_MODE)
-#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_MDIV)
-#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
- (STARTUP_HCLKDIV + 1))
-#else
-#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_AMDIV)
-#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
- (STARTUP_HCLKDIV + 1))
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */
-#define DMC1_MEM_CFG2 0xB45
-#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
-#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
-
-/* Memory Parameters */
-/* DDR Parameters */
-#define DDR_tREFRESH 7800 /* ns */
-#define DDR_tRAS 45 /* ns (min: 45ns)*/
-#define DDR_tRC 68 /* ns (min: 67.5ns)*/
-#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
-#define DDR_tRFC 80 /* ns (min: 80ns)*/
-#define DDR_tRP 23 /* ns (min: 22.5ns)*/
-#define DDR_tRRD 15 /* ns (min: 15ns)*/
-#define DDR_tWR 15 /* ns (min: 15ns)*/
-#define DDR_tXSR 120 /* ns (min: 120ns)*/
-#define DDR_CASL 3 /* CAS Latency 3 */
-
-/*
- * mDDR memory configuration
- */
-
-#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000)
-
-#define DMC_DDR_BA_EMRS 2
-#define DMC_DDR_MEM_CASLAT 3
-/* 6 Set Cas Latency to 3 */
-#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1)
-/* Min 0.75 ~ 1.25 */
-#define DMC_DDR_t_DQSS 1
-/* Min 2 tck */
-#define DMC_DDR_t_MRD 2
-/* 7, Min 45ns */
-#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1)
-/* 10, Min 67.5ns */
-#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1)
-/* 4,5(TRM), Min 22.5ns */
-#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1)
-#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3)
-/* 11,18(TRM) Min 80ns */
-#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1)
-#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5)
-/* 4, 5(TRM) Min 22.5ns */
-#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1)
-#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3)
-/* 3, Min 15ns */
-#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1)
-/* Min 15ns */
-#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1)
-#define DMC_DDR_t_WTR 2
-/* 1tck + tIS(1.5ns) */
-#define DMC_DDR_t_XP 2
-/* 17, Min 120ns */
-#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1)
-#define DMC_DDR_t_ESR DMC_DDR_t_XSR
-/* TRM 2656 */
-#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH))
-/* 2b01 : mDDR */
-#define DMC_DDR_USER_CONFIG 1
-
-#ifndef __ASSEMBLY__
-enum s3c64xx_uarts_nr {
- S3C64XX_UART0,
- S3C64XX_UART1,
- S3C64XX_UART2,
-};
-
-#include "s3c64x0.h"
-
-static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr)
-{
- return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400));
-}
-#endif
-
-#endif /*__S3C6400_H__*/
+++ /dev/null
-/*
- * (C) Copyright 2003
- * David MÃŒller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME : S3C64XX.h
- * Version : 31.3.2003
- *
- * common stuff for SAMSUNG S3C64XX SoC
- ************************************************/
-
-#ifndef __S3C64XX_H__
-#define __S3C64XX_H__
-
-#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400)
-#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration!
-#endif
-
-#include <asm/types.h>
-
-/* UART (see manual chapter 11) */
-typedef struct {
- volatile u32 ULCON;
- volatile u32 UCON;
- volatile u32 UFCON;
- volatile u32 UMCON;
- volatile u32 UTRSTAT;
- volatile u32 UERSTAT;
- volatile u32 UFSTAT;
- volatile u32 UMSTAT;
-#ifdef __BIG_ENDIAN
- volatile u8 res1[3];
- volatile u8 UTXH;
- volatile u8 res2[3];
- volatile u8 URXH;
-#else /* Little Endian */
- volatile u8 UTXH;
- volatile u8 res1[3];
- volatile u8 URXH;
- volatile u8 res2[3];
-#endif
- volatile u32 UBRDIV;
-#ifdef __BIG_ENDIAN
- volatile u8 res3[2];
- volatile u16 UDIVSLOT;
-#else
- volatile u16 UDIVSLOT;
- volatile u8 res3[2];
-#endif
-} s3c64xx_uart;
-
-/* PWM TIMER (see manual chapter 10) */
-typedef struct {
- volatile u32 TCNTB;
- volatile u32 TCMPB;
- volatile u32 TCNTO;
-} s3c64xx_timer;
-
-typedef struct {
- volatile u32 TCFG0;
- volatile u32 TCFG1;
- volatile u32 TCON;
- s3c64xx_timer ch[4];
- volatile u32 TCNTB4;
- volatile u32 TCNTO4;
-} s3c64xx_timers;
-
-#endif /*__S3C64XX_H__*/
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