prompt "Target select"
optional
-config TARGET_RSK7203
- bool "RSK+ 7203"
- select CPU_SH2A
-
config TARGET_RSK7264
bool "RSK2+SH7264"
select CPU_SH2A
source "board/renesas/r0p7734/Kconfig"
source "board/renesas/r2dplus/Kconfig"
source "board/renesas/r7780mp/Kconfig"
-source "board/renesas/rsk7203/Kconfig"
source "board/renesas/rsk7264/Kconfig"
source "board/renesas/rsk7269/Kconfig"
source "board/renesas/sh7752evb/Kconfig"
+++ /dev/null
-if TARGET_RSK7203
-
-config SYS_BOARD
- default "rsk7203"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "rsk7203"
-
-endif
+++ /dev/null
-RSK7203 BOARD
-M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
-M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-S: Maintained
-F: board/renesas/rsk7203/
-F: include/configs/rsk7203.h
-F: configs/rsk7203_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
-# Copyright (C) 2008 Renesas Solutions Corp.
-#
-# u-boot/board/rsk7203/Makefile
-#
-
-obj-y := rsk7203.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Renesas Solutions Corp.
- */
-#include <config.h>
-
-#include <asm/processor.h>
-#include <asm/macro.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
- /* Cache setting */
- write32 CCR1_A ,CCR1_D
-
- /* ConfigurePortPins */
- write16 PECRL3_A, PECRL3_D
-
- write16 PCCRL4_A, PCCRL4_D0
-
- write16 PECRL4_A, PECRL4_D0
-
- write16 PEIORL_A, PEIORL_D0
-
- write16 PCIORL_A, PCIORL_D
-
- write16 PFCRH2_A, PFCRH2_D
-
- write16 PFCRH3_A, PFCRH3_D
-
- write16 PFCRH1_A, PFCRH1_D
-
- write16 PFIORH_A, PFIORH_D
-
- write16 PECRL1_A, PECRL1_D0
-
- write16 PEIORL_A, PEIORL_D1
-
- /* Configure Operating Frequency */
- write16 WTCSR_A, WTCSR_D0
-
- write16 WTCSR_A, WTCSR_D1
-
- write16 WTCNT_A, WTCNT_D
-
- /* Set clock mode*/
- write16 FRQCR_A, FRQCR_D
-
- /* Configure Bus And Memory */
-init_bsc_cs0:
- write16 PCCRL4_A, PCCRL4_D1
-
- write16 PECRL1_A, PECRL1_D1
-
- write32 CMNCR_A, CMNCR_D
-
- write32 CS0BCR_A, CS0BCR_D
-
- write32 CS0WCR_A, CS0WCR_D
-
-init_bsc_cs1:
- write16 PECRL4_A, PECRL4_D1
-
- write32 CS1WCR_A, CS1WCR_D
-
-init_sdram:
- write16 PCCRL2_A, PCCRL2_D
-
- write16 PCCRL4_A, PCCRL4_D2
-
- write16 PCCRL1_A, PCCRL1_D
-
- write16 PCCRL3_A, PCCRL3_D
-
- write32 CS3BCR_A, CS3BCR_D
-
- write32 CS3WCR_A, CS3WCR_D
-
- write32 SDCR_A, SDCR_D
-
- write32 RTCOR_A, RTCOR_D
-
- write32 RTCSR_A, RTCSR_D
-
- /* wait 200us */
- mov.l REPEAT_D, r3
- mov #0, r2
-repeat0:
- add #1, r2
- cmp/hs r3, r2
- bf repeat0
- nop
-
- mov.l SDRAM_MODE, r1
- mov #0, r0
- mov.l r0, @r1
-
- nop
- rts
-
- .align 4
-
-CCR1_A: .long CCR1
-CCR1_D: .long 0x0000090B
-PCCRL4_A: .long 0xFFFE3910
-PCCRL4_D0: .word 0x0000
-.align 2
-PECRL4_A: .long 0xFFFE3A10
-PECRL4_D0: .word 0x0000
-.align 2
-PECRL3_A: .long 0xFFFE3A12
-PECRL3_D: .word 0x0000
-.align 2
-PEIORL_A: .long 0xFFFE3A06
-PEIORL_D0: .word 0x1C00
-PEIORL_D1: .word 0x1C02
-PCIORL_A: .long 0xFFFE3906
-PCIORL_D: .word 0x4000
-.align 2
-PFCRH2_A: .long 0xFFFE3A8C
-PFCRH2_D: .word 0x0000
-.align 2
-PFCRH3_A: .long 0xFFFE3A8A
-PFCRH3_D: .word 0x0000
-.align 2
-PFCRH1_A: .long 0xFFFE3A8E
-PFCRH1_D: .word 0x0000
-.align 2
-PFIORH_A: .long 0xFFFE3A84
-PFIORH_D: .word 0x0729
-.align 2
-PECRL1_A: .long 0xFFFE3A16
-PECRL1_D0: .word 0x0033
-.align 2
-
-
-WTCSR_A: .long 0xFFFE0000
-WTCSR_D0: .word 0xA518
-WTCSR_D1: .word 0xA51D
-WTCNT_A: .long 0xFFFE0002
-WTCNT_D: .word 0x5A84
-.align 2
-FRQCR_A: .long 0xFFFE0010
-FRQCR_D: .word 0x0104
-.align 2
-
-PCCRL4_D1: .word 0x0010
-PECRL1_D1: .word 0x0133
-
-CMNCR_A: .long 0xFFFC0000
-CMNCR_D: .long 0x00001810
-CS0BCR_A: .long 0xFFFC0004
-CS0BCR_D: .long 0x10000400
-CS0WCR_A: .long 0xFFFC0028
-CS0WCR_D: .long 0x00000B41
-PECRL4_D1: .word 0x0100
-.align 2
-CS1WCR_A: .long 0xFFFC002C
-CS1WCR_D: .long 0x00000B01
-PCCRL4_D2: .word 0x0011
-.align 2
-PCCRL3_A: .long 0xFFFE3912
-PCCRL3_D: .word 0x0011
-.align 2
-PCCRL2_A: .long 0xFFFE3914
-PCCRL2_D: .word 0x1111
-.align 2
-PCCRL1_A: .long 0xFFFE3916
-PCCRL1_D: .word 0x1010
-.align 2
-PDCRL4_A: .long 0xFFFE3990
-PDCRL4_D: .word 0x0011
-.align 2
-PDCRL3_A: .long 0xFFFE3992
-PDCRL3_D: .word 0x00011
-.align 2
-PDCRL2_A: .long 0xFFFE3994
-PDCRL2_D: .word 0x1111
-.align 2
-PDCRL1_A: .long 0xFFFE3996
-PDCRL1_D: .word 0x1000
-.align 2
-CS3BCR_A: .long 0xFFFC0010
-CS3BCR_D: .long 0x00004400
-CS3WCR_A: .long 0xFFFC0034
-CS3WCR_D: .long 0x00002892
-SDCR_A: .long 0xFFFC004C
-SDCR_D: .long 0x00000809
-RTCOR_A: .long 0xFFFC0058
-RTCOR_D: .long 0xA55A0041
-RTCSR_A: .long 0xFFFC0050
-RTCSR_D: .long 0xa55a0010
-
-SDRAM_MODE: .long 0xFFFC5040
-REPEAT_D: .long 0x00009C40
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Renesas Solutions Corp.
- *
- * u-boot/board/rsk7203/rsk7203.c
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-int checkboard(void)
-{
- puts("BOARD: Renesas Technology RSK7203\n");
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-void led_set_state(unsigned short value)
-{
-}
-
-/*
- * The RSK board has the SMSC9118 wired up 'incorrectly'.
- * Byte-swapping is necessary, and so poor performance is inevitable.
- * This problem cannot evade by the swap function of CHIP, this can
- * evade by software Byte-swapping.
- * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
- * functions necessary to solve this problem.
- */
-u32 pkt_data_pull(struct eth_device *dev, u32 addr)
-{
- volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
- return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
- | swab16(*(addr_16 + 1));
-}
-
-void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
-{
- addr += dev->iobase;
- *(volatile u16 *)(addr + 2) = swab16((u16)val);
- *(volatile u16 *)(addr) = swab16((u16)(val >> 16));
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0xC7C0000
-CONFIG_TARGET_RSK7203=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_AUTOBOOT is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-# CONFIG_CMD_MISC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas Technology RSK 7203
- *
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Renesas Solutions Corp.
- */
-
-#ifndef __RSK7203_H
-#define __RSK7203_H
-
-#define CONFIG_CPU_SH7203 1
-
-#define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
-
-#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-/* MEMORY */
-#define RSK7203_SDRAM_BASE 0x0C000000
-#define RSK7203_FLASH_BASE_1 0x20000000 /* Non cache */
-#define RSK7203_FLASH_BANK_SIZE (4 * 1024 * 1024)
-
-/* List of legal baudrate settings for this board */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF0 1
-
-#define CONFIG_SYS_MEMTEST_START RSK7203_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024))
-
-#define CONFIG_SYS_SDRAM_BASE RSK7203_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
-#define CONFIG_SYS_MONITOR_BASE RSK7203_FLASH_BASE_1
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* FLASH */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_BASE RSK7203_FLASH_BASE_1
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_SECT 64
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
-#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
-
-#endif /* __RSK7203_H */
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